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yosys/techlibs/anlogic/lutrams.txt
2022-05-18 17:32:56 +02:00

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ram distributed $__ANLOGIC_DRAM16X4_ {
abits 4;
width 4;
cost 4;
init no_undef;
prune_rom;
port sw "W" {
clock posedge;
}
port ar "R" {
}
}