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- Use `:file:` role for file names, as well as `:makevar:` and `:program:`. - Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets. - Add link to ABC. - More (and better) links to code examples. Formatted `:file:` text with link to source on github. - Includes a few extra todos (mostly picking up inline code blocks and a couple intro reminders). - Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags. - Reflowing some paragraphs for spacing/width.
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20 lines
466 B
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Internal flow
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=============
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A (usually short) synthesis script controls Yosys.
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These scripts contain three types of commands:
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- **Frontends**, that read input files (usually Verilog);
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- **Passes**, that perform transformations on the design in memory;
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- **Backends**, that write the design in memory to a file (various formats are
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available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).
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.. toctree::
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:maxdepth: 3
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overview
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control_and_data
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verilog_frontend
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