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https://github.com/YosysHQ/yosys
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dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
5 lines
105 B
Verilog
5 lines
105 B
Verilog
module primetest(p, a, b, ok);
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input [15:0] p, a, b;
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output ok = p != a*b || a == 1 || b == 1;
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endmodule
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