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arith_map.v
|
gowin: Fix X output of $alu techmap
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2023-05-01 17:56:41 +02:00 |
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brams.txt
|
gowin: Change BYTE ENABLE handling.
|
2024-01-27 17:19:49 +10:00 |
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brams_map.v
|
gowin: Fix SDP write enable port.
|
2024-01-30 17:06:59 +10:00 |
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cells_map.v
|
gowin: add mux techmap and whitebox
|
2023-10-12 20:24:12 +08:00 |
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cells_sim.v
|
Merge aa86e6355e into a0e94e506d
|
2025-05-06 12:08:27 -04:00 |
|
cells_xtra.py
|
Gowin. Remove unnecessary modules
|
2025-03-28 06:34:26 +10:00 |
|
cells_xtra_gw1n.v
|
Gowin. Remove unnecessary modules
|
2025-03-28 06:34:26 +10:00 |
|
cells_xtra_gw2a.v
|
Gowin. Remove unnecessary modules
|
2025-03-28 06:34:26 +10:00 |
|
cells_xtra_gw5a.v
|
Gowin. Remove unnecessary modules
|
2025-03-28 06:34:26 +10:00 |
|
lutrams.txt
|
gowin: Use memory_libmap pass.
|
2022-05-18 17:32:56 +02:00 |
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lutrams_map.v
|
gowin: Use memory_libmap pass.
|
2022-05-18 17:32:56 +02:00 |
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Makefile.inc
|
gowin: split cells_xtra by family
|
2024-11-26 15:42:22 +01:00 |
|
synth_gowin.cc
|
gowin: split cells_xtra by family
|
2024-11-26 15:42:22 +01:00 |
