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35 lines
782 B
Text
35 lines
782 B
Text
read_verilog <<EOF
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module top(input clk, rst, input [7:0] din, output [7:0] dout, input bin, output bout);
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reg [7:0] dq;
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reg bq;
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always @(posedge clk, posedge rst) begin
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if (rst) dq <= '0;
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else dq <= din;
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end
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always @(posedge clk) bq <= bin;
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assign dout = dq;
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assign bout = bq;
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endmodule
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EOF
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proc
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hierarchy -top top
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select -assert-count 1 t:$dff
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select -assert-count 1 t:$adff
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select -assert-count 0 t:$dff n:bq %i
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select -assert-count 0 t:$adff n:dq %i
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select -assert-count 1 w:bq
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select -assert-count 1 w:dq
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rename -wire -move-to-cell
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select -assert-count 1 t:$dff
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select -assert-count 1 t:$adff
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select -assert-count 1 t:$dff n:bq %i
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select -assert-count 1 t:$adff n:dq %i
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select -assert-count 0 w:bq
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select -assert-count 0 w:dq
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