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49 lines
1.4 KiB
Text
49 lines
1.4 KiB
Text
read_rtlil procs.il
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select -assert-count 2 p:*
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design -stash err_q
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# processes get removed by default
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design -load err_q
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bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
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select -assert-none p:*
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# individual processes can be kept
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design -load err_q
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setattr -set bugpoint_keep 1 p:proc_a
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bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
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select -assert-count 1 p:*
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# all processes can be kept
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design -load err_q
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bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -wires
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select -assert-count 2 p:*
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# d and clock are connected after proc
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design -load err_q
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proc
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select -assert-count 3 w:d %co
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select -assert-count 3 w:clock %co
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# no assigns means no d
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design -load err_q
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bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -assigns
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proc
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select -assert-count 1 w:d %co
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# no updates means no clock
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design -load err_q
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bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -updates
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proc
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select -assert-count 1 w:clock %co
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# can remove ports
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design -load err_q
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select -assert-count 5 x:*
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bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
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select -assert-none x:*
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# can keep ports
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design -load err_q
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setattr -set bugpoint_keep 1 i:d o:q
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bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
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select -assert-count 2 x:*
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