mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
20 lines
776 B
Plaintext
20 lines
776 B
Plaintext
read_verilog ../common/dffs.v
|
|
design -save read
|
|
|
|
hierarchy -top dff
|
|
proc
|
|
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd dff # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:FD1P3IX
|
|
select -assert-none t:FD1P3IX t:IB t:OB t:VHI t:VLO %% t:* %D
|
|
|
|
design -load read
|
|
hierarchy -top dffe
|
|
proc
|
|
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd dffe # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:FD1P3IX
|
|
select -assert-none t:FD1P3IX t:IB t:OB t:VHI t:VLO %% t:* %D
|