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yosys/backends
whitequark 4d40595d64 cxxrtl: make alias analysis outlining-aware.
Before this commit, if a sequence of wires assigned in a chain would
terminate on a cell, none of the wires would get marked as aliases,
and typically all of the public wires would get outlined. The reason
for this behavior is that alias analysis predates outlining and in
fact runs before it.

After this commit, alias analysis runs after outlining and considers
outlined wires valid aliasees. More importantly, if the chained wires
contain any valid aliasees, then all of the wires are aliased to
the one that is topologically deepest.

Aliased wires incur virtually no overhead for the VCD writer, unlike
outlined wires that would otherwise take their place. On Minerva SoC
SRAM, size of the full VCD dump is reduced by ~65%, and throughput
is increased by ~55%.
2020-12-15 11:02:38 +00:00
..
aiger use the new isPublic() in a few places 2020-09-14 12:43:18 +02:00
blif backends/blif: Remove unused vector of strings (#2420) 2020-11-16 09:31:48 +01:00
btor btor: Use Mem helper. 2020-10-21 17:51:20 +02:00
cxxrtl cxxrtl: make alias analysis outlining-aware. 2020-12-15 11:02:38 +00:00
edif use the new isPublic() in a few places 2020-09-14 12:43:18 +02:00
firrtl Formatting fixes 2020-11-23 10:55:09 +01:00
intersynth Replace "ILANG" with "RTLIL" everywhere. 2020-08-26 17:29:32 +00:00
json Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
protobuf Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
rtlil Replace "ILANG" with "RTLIL" everywhere. 2020-08-26 17:29:32 +00:00
simplec Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
smt2 smt2: Use Mem helper. 2020-10-21 17:51:20 +02:00
smv Add missing gitignores for test artifacts 2020-08-31 19:43:51 +02:00
spice Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
table Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
verilog Add verilog backend option for simple_lhs 2020-11-25 18:21:41 +01:00