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yosys/techlibs
2026-07-20 15:01:30 +02:00
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achronix
analogdevices
anlogic WIP migration to twine 2026-07-20 12:27:18 +02:00
common WIP 2026-07-20 12:27:17 +02:00
coolrunner2 coolrunner2: twines 2026-07-20 15:01:30 +02:00
easic
efinix WIP migration to twine 2026-07-20 12:27:18 +02:00
fabulous Remove old techmap. 2026-07-08 12:07:58 +02:00
gatemate WIP migration to twine 2026-07-20 12:27:18 +02:00
gowin gowin: replace positional arguments in cells_sim.v with named 2026-07-17 23:33:02 +02:00
greenpak4 WIP migration to twine 2026-07-20 12:27:18 +02:00
ice40 twine: fix replayability, reduce TwineSearch usage 2026-07-20 13:57:10 +02:00
intel Revert "intel: register bram celltypes" 2026-07-17 23:38:01 +02:00
intel_alm Revert "intel: register bram celltypes" 2026-07-17 23:38:01 +02:00
lattice WIP 2026-07-20 12:27:17 +02:00
microchip WIP migration to twine 2026-07-20 12:27:18 +02:00
nanoxplore techlibs: fix twines 2026-07-20 13:57:10 +02:00
quicklogic techlibs: fix twines 2026-07-20 13:57:10 +02:00
sf2
xilinx WIP migration to twine 2026-07-20 12:27:18 +02:00
CMakeLists.txt
fix_mod.py