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https://github.com/YosysHQ/yosys
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95 lines
3 KiB
Text
95 lines
3 KiB
Text
read_verilog <<EOT
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module split_output (A, B, Y, magic);
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input [1:0] A;
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input [1:0] B;
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output [1:0] Y;
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input magic;
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wire W;
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assign Y = A + B;
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assign W = Y[0]; // <--- look here
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endmodule
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EOT
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proc
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design -save split_output
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# Basic -value test
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abstract -value -enable magic w:W
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check -assert
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# Connections to $add Y output port
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select -set conn_to_y t:$add %x:+[Y] t:$add %d
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# The $add Y output port feeds partially into a mux
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select -set mux @conn_to_y %ci t:$mux %i
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select -assert-count 1 @mux
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# and also the Y module output
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select -assert-count 1 @conn_to_y %a o:Y %i
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# The S input port is fed with the magic wire
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select -assert-count 1 @mux %x:+[S] w:magic %i
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# The B input port is fed with an anyseq
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select -assert-count 1 @mux %x:+[B] %ci t:$anyseq %i
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# The Y output port feeds into the Y module output
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select -assert-count 1 @mux %x:+[Y] %co o:Y %i
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# -----------------------------------------------------------------------------
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# Same thing, but we use -slice instead of wire W
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design -reset
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read_verilog <<EOT
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module split_output_no_w (A, B, Y, magic);
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input [1:0] A;
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input [1:0] B;
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output [1:0] Y;
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input magic;
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assign Y = A + B;
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endmodule
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EOT
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proc
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# Same test as the previous case
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abstract -value -enable magic -slice 0 w:Y
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check -assert
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select -set conn_to_y t:$add %x:+[Y] t:$add %d
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select -set mux @conn_to_y %ci t:$mux %i
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select -assert-count 1 @mux
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select -assert-count 1 @conn_to_y %a o:Y %i
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select -assert-count 1 @mux %x:+[S] w:magic %i
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select -assert-count 1 @mux %x:+[B] %ci t:$anyseq %i
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select -assert-count 1 @mux %x:+[Y] %co o:Y %i
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# -----------------------------------------------------------------------------
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design -reset
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read_verilog <<EOT
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module split_input (A, B, Y, magic);
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input [1:0] A;
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input [1:0] B;
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output [1:0] Y;
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input magic;
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wire W;
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assign Y = A + B;
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assign W = A[0]; // <--- look here
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endmodule
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EOT
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proc
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design -save split_input
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# The mux goes on an input this time
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abstract -value -enable magic w:W
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check -assert
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# Connections to add A input port
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select -set conn_to_a t:$add %x:+[A] t:$add %d
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# The B input port is partially fed with a mux
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select -set mux @conn_to_a %ci t:$mux %i
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select -assert-count 1 @mux
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# and also the A input
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select -assert-count 1 @conn_to_a %a w:A %i
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# The S input port is fed with the magic wire
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select -assert-count 1 @mux %x:+[S] w:magic %i
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# The A input port is fed with the module input A
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select -assert-count 1 @mux %x:+[A] %ci i:A %i
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# The B input port is fed with an anyseq
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select -assert-count 1 @mux %x:+[B] %ci t:$anyseq %i
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# -----------------------------------------------------------------------------
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# All wires selected, excluding magic -> muxes on inputs and outputs
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design -load split_output
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select -assert-count 0 t:$mux
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abstract -value -enable magic w:* w:magic %d
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select -assert-count 3 t:$mux
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# All cells selected -> muxes on outputs only
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design -load split_output
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select -assert-count 0 t:$mux
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abstract -value -enable magic t:*
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select -assert-count 1 t:$mux
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# -----------------------------------------------------------------------------
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