mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
995 lines
31 KiB
C++
995 lines
31 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/log_help.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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#include "kernel/modtools.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Finds signal values with known constant or known unused values in the initial state
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struct InitValWorker
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{
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Module *module;
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ModWalker modwalker;
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SigMap &sigmap;
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FfInitVals initvals;
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dict<RTLIL::SigBit, RTLIL::State> initconst_bits;
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dict<RTLIL::SigBit, bool> used_bits;
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InitValWorker(Module *module) : module(module), modwalker(module->design), sigmap(modwalker.sigmap)
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{
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modwalker.setup(module);
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initvals.set(&modwalker.sigmap, module);
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for (auto wire : module->wires())
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if (wire->name.isPublic() || wire->get_bool_attribute(ID::keep))
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for (auto bit : SigSpec(wire))
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used_bits[sigmap(bit)] = true;
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}
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// Sign/Zero-extended indexing of individual port bits
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static SigBit bit_in_port(RTLIL::Cell *cell, RTLIL::IdString port, RTLIL::IdString sign, int index)
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{
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auto sig_port = cell->getPort(port);
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if (index < GetSize(sig_port))
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return sig_port[index];
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else if (cell->getParam(sign).as_bool())
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return GetSize(sig_port) > 0 ? sig_port[GetSize(sig_port) - 1] : State::Sx;
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else
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return State::S0;
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}
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// Has the signal a known constant value in the initial state?
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//
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// For sync-only FFs outputs, this is their initval. For logic loops,
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// multiple drivers or unknown cells this is Sx. For a small number of
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// handled cells we recurse through their inputs. All results are cached.
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RTLIL::State initconst(SigBit bit)
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{
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sigmap.apply(bit);
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if (!bit.is_wire())
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return bit.data;
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auto it = initconst_bits.find(bit);
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if (it != initconst_bits.end())
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return it->second;
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// Setting this temporarily to x takes care of any logic loops
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initconst_bits[bit] = State::Sx;
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pool<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, {bit});
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if (portbits.size() != 1)
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return State::Sx;
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ModWalker::PortBit portbit = *portbits.begin();
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RTLIL::Cell *cell = portbit.cell;
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if (cell->is_builtin_ff())
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{
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FfData ff(&initvals, cell);
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if (ff.has_aload || ff.has_sr || ff.has_arst || (!ff.has_clk && !ff.has_gclk)) {
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for (auto bit_q : ff.sig_q) {
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initconst_bits[sigmap(bit_q)] = State::Sx;
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}
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return State::Sx;
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}
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for (int i = 0; i < ff.width; i++) {
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initconst_bits[sigmap(ff.sig_q[i])] = ff.val_init[i];
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}
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return ff.val_init[portbit.offset];
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}
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if (cell->type.in(ID($mux), ID($and), ID($or), ID($eq), ID($eqx), ID($initstate)))
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{
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if (cell->type == ID($mux))
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{
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SigBit sig_s = sigmap(cell->getPort(ID::S));
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State init_s = initconst(sig_s);
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State init_y;
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if (init_s == State::S0) {
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init_y = initconst(cell->getPort(ID::A)[portbit.offset]);
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} else if (init_s == State::S1) {
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init_y = initconst(cell->getPort(ID::B)[portbit.offset]);
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} else {
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State init_a = initconst(cell->getPort(ID::A)[portbit.offset]);
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State init_b = initconst(cell->getPort(ID::B)[portbit.offset]);
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init_y = init_a == init_b ? init_a : State::Sx;
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}
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initconst_bits[bit] = init_y;
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return init_y;
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}
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if (cell->type.in(ID($and), ID($or)))
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{
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State init_a = initconst(bit_in_port(cell, ID::A, ID::A_SIGNED, portbit.offset));
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State init_b = initconst(bit_in_port(cell, ID::B, ID::B_SIGNED, portbit.offset));
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State init_y;
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if (init_a == init_b)
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init_y = init_a;
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else if (cell->type == ID($and) && (init_a == State::S0 || init_b == State::S0))
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init_y = State::S0;
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else if (cell->type == ID($or) && (init_a == State::S1 || init_b == State::S1))
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init_y = State::S1;
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else
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init_y = State::Sx;
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initconst_bits[bit] = init_y;
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return init_y;
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}
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if (cell->type.in(ID($eq), ID($eqx))) // Treats $eqx as $eq
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{
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if (portbit.offset > 0) {
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initconst_bits[bit] = State::S0;
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return State::S0;
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}
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_b = cell->getPort(ID::B);
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State init_y = State::S1;
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for (int i = 0; init_y != State::S0 && i < GetSize(sig_a); i++) {
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State init_ai = initconst(bit_in_port(cell, ID::A, ID::A_SIGNED, i));
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if (init_ai == State::Sx) {
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init_y = State::Sx;
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continue;
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}
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State init_bi = initconst(bit_in_port(cell, ID::B, ID::B_SIGNED, i));
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if (init_bi == State::Sx)
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init_y = State::Sx;
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else if (init_ai != init_bi)
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init_y = State::S0;
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}
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initconst_bits[bit] = init_y;
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return init_y;
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}
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if (cell->type == ID($initstate))
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{
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initconst_bits[bit] = State::S1;
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return State::S1;
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}
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log_assert(false);
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}
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return State::Sx;
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}
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RTLIL::Const initconst(SigSpec sig)
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{
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std::vector<RTLIL::State> bits;
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for (auto bit : sig)
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bits.push_back(initconst(bit));
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return bits;
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}
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// Is the initial value of this signal used?
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//
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// An initial value of a signal is considered as used if it a) aliases a
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// wire with a public name, an output wire or with a keep attribute b)
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// combinationally drives such a wire or c) drive an input to an unknown
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// cell.
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//
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// This recurses into driven cells for a small number of known handled
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// celltypes. Results are cached and initconst is used to detect unused
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// inputs for the handled celltypes.
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bool is_initval_used(SigBit bit)
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{
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if (!bit.is_wire())
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return false;
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auto it = used_bits.find(bit);
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if (it != used_bits.end())
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return it->second;
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used_bits[bit] = true; // Temporarily set to guard against logic loops
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pool<ModWalker::PortBit> portbits;
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modwalker.get_consumers(portbits, {bit});
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for (auto portbit : portbits) {
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RTLIL::Cell *cell = portbit.cell;
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if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !cell->is_builtin_ff()) {
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return true;
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}
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}
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for (auto portbit : portbits)
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{
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RTLIL::Cell *cell = portbit.cell;
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if (cell->is_builtin_ff())
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{
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FfData ff(&initvals, cell);
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if (ff.has_aload || ff.has_sr || ff.has_arst || ff.has_gclk || !ff.has_clk)
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return true;
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if (ff.has_ce && initconst(ff.sig_ce.as_bit()) == (ff.pol_ce ? State::S0 : State::S1))
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continue;
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if (ff.has_srst && initconst(ff.sig_srst.as_bit()) == (ff.pol_srst ? State::S1 : State::S0))
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continue;
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return true;
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}
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else if (cell->type == ID($mux))
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{
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State init_s = initconst(cell->getPort(ID::S).as_bit());
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if (init_s == State::S0 && portbit.port == ID::B)
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continue;
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if (init_s == State::S1 && portbit.port == ID::A)
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continue;
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auto sig_y = cell->getPort(ID::Y);
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if (is_initval_used(sig_y[portbit.offset]))
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return true;
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}
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else if (cell->type.in(ID($and), ID($or)))
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{
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auto sig_a = cell->getPort(ID::A);
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auto sig_b = cell->getPort(ID::B);
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auto sig_y = cell->getPort(ID::Y);
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if (GetSize(sig_y) != GetSize(sig_a) || GetSize(sig_y) != GetSize(sig_b))
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return true; // TODO handle more of this
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State absorbing = cell->type == ID($and) ? State::S0 : State::S1;
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if (portbit.port == ID::A && initconst(sig_b[portbit.offset]) == absorbing)
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continue;
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if (portbit.port == ID::B && initconst(sig_a[portbit.offset]) == absorbing)
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continue;
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if (is_initval_used(sig_y[portbit.offset]))
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return true;
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}
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else if (cell->type == ID($mem_v2))
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{
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// TODO Use mem.h instead to uniformily cover all cases, most
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// likely requires processing all memories when initializing
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// the worker
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if (!portbit.port.in(ID::WR_DATA, ID::WR_ADDR, ID::RD_ADDR))
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return true;
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if (portbit.port == ID::WR_DATA)
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{
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if (initconst(cell->getPort(ID::WR_EN)[portbit.offset]) == State::S0)
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continue;
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}
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else if (portbit.port == ID::WR_ADDR)
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{
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int port = portbit.offset / cell->getParam(ID::ABITS).as_int();
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auto sig_en = cell->getPort(ID::WR_EN);
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int width = cell->getParam(ID::WIDTH).as_int();
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for (int i = port * width; i < (port + 1) * width; i++)
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if (initconst(sig_en[i]) != State::S0)
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return true;
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continue;
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}
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else if (portbit.port == ID::RD_ADDR)
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{
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int port = portbit.offset / cell->getParam(ID::ABITS).as_int();
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auto sig_en = cell->getPort(ID::RD_EN);
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if (initconst(sig_en[port]) != State::S0)
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return true;
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continue;
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}
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else
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return true;
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}
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else
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log_assert(false);
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}
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used_bits[bit] = false;
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return false;
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}
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};
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struct ReplacedPort {
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IdString name;
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int offset;
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bool clk_pol;
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};
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struct HierarchyWorker
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{
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Design *design;
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pool<Module *> pending;
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dict<Module *, std::vector<ReplacedPort>> replaced_clk_inputs;
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HierarchyWorker(Design *design) :
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design(design)
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{
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for (auto module : design->modules())
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pending.insert(module);
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}
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void propagate();
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const std::vector<ReplacedPort> &find_replaced_clk_inputs(IdString cell_type);
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};
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// Propagates replaced clock signals
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struct PropagateWorker
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{
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HierarchyWorker &hierarchy;
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Module *module;
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SigMap sigmap;
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dict<SigBit, bool> replaced_clk_bits;
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dict<SigBit, SigBit> not_drivers;
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std::vector<ReplacedPort> replaced_clk_inputs;
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std::vector<std::pair<SigBit, bool>> pending;
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PropagateWorker(Module *module, HierarchyWorker &hierarchy) :
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hierarchy(hierarchy), module(module), sigmap(module)
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{
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hierarchy.pending.erase(module);
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for (auto wire : module->wires())
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if (wire->has_attribute(ID::replaced_by_gclk))
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replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].at(0) == State::S1, false);
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($not), ID($_NOT_))) {
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auto sig_a = cell->getPort(ID::A);
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auto &sig_y = cell->getPort(ID::Y);
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sig_a.extend_u0(GetSize(sig_y), cell->hasParam(ID::A_SIGNED) && cell->parameters.at(ID::A_SIGNED).as_bool());
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for (int i = 0; i < GetSize(sig_a); i++)
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if (sig_a[i].is_wire())
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not_drivers.emplace(sigmap(sig_y[i]), sigmap(sig_a[i]));
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} else {
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for (auto &port_bit : hierarchy.find_replaced_clk_inputs(cell->type))
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replace_clk_bit(cell->getPort(port_bit.name)[port_bit.offset], port_bit.clk_pol, true);
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}
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}
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while (!pending.empty()) {
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auto current = pending.back();
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pending.pop_back();
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auto it = not_drivers.find(current.first);
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if (it == not_drivers.end())
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continue;
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replace_clk_bit(it->second, !current.second, true);
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}
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($not), ID($_NOT_)))
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continue;
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for (auto &conn : cell->connections()) {
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if (!cell->output(conn.first))
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continue;
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for (SigBit bit : conn.second) {
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sigmap.apply(bit);
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if (replaced_clk_bits.count(bit))
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log_error("derived signal %s driven by %s (%s) from module %s is used as clock, derived clocks are only supported with clk2fflogic.\n",
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log_signal(bit), log_id(cell->name), log_id(cell->type), log_id(module));
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}
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}
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}
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for (auto port : module->ports) {
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auto wire = module->wire(port);
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if (!wire->port_input)
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continue;
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for (int i = 0; i < GetSize(wire); i++) {
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SigBit bit(wire, i);
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sigmap.apply(bit);
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auto it = replaced_clk_bits.find(bit);
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if (it == replaced_clk_bits.end())
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continue;
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replaced_clk_inputs.emplace_back(ReplacedPort {port, i, it->second});
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if (it->second) {
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bit = module->Not(NEW_ID, bit);
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}
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}
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}
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}
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void replace_clk_bit(SigBit bit, bool polarity, bool add_attribute)
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{
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sigmap.apply(bit);
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if (!bit.is_wire())
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log_error("XXX todo\n");
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auto it = replaced_clk_bits.find(bit);
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if (it != replaced_clk_bits.end()) {
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if (it->second != polarity)
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log_error("signal %s from module %s is used as clock with different polarities, run clk2fflogic instead.\n",
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log_signal(bit), log_id(module));
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return;
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}
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replaced_clk_bits.emplace(bit, polarity);
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if (add_attribute) {
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Wire *clk_wire = bit.wire;
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if (bit.offset != 0 || GetSize(bit.wire) != 1) {
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clk_wire = module->addWire(NEW_ID);
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module->connect(RTLIL::SigBit(clk_wire), bit);
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}
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clk_wire->attributes[ID::replaced_by_gclk] = polarity ? State::S1 : State::S0;
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clk_wire->set_bool_attribute(ID::keep);
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}
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pending.emplace_back(bit, polarity);
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}
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};
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const std::vector<ReplacedPort> &HierarchyWorker::find_replaced_clk_inputs(IdString cell_type)
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{
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static const std::vector<ReplacedPort> empty;
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if (!cell_type.isPublic())
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return empty;
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Module *module = design->module(cell_type);
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if (module == nullptr)
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return empty;
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auto it = replaced_clk_inputs.find(module);
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if (it != replaced_clk_inputs.end())
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return it->second;
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if (pending.count(module)) {
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PropagateWorker worker(module, *this);
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return replaced_clk_inputs.emplace(module, std::move(worker.replaced_clk_inputs)).first->second;
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}
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return empty;
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}
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void HierarchyWorker::propagate()
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{
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while (!pending.empty())
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PropagateWorker worker(pending.pop(), *this);
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}
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struct FormalFfPass : public Pass {
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FormalFfPass() : Pass("formalff", "prepare FFs for formal") { }
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bool formatted_help() override {
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auto *help = PrettyHelp::get_current();
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help->set_group("formal");
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return false;
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}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" formalff [options] [selection]\n");
|
|
log("\n");
|
|
log("This pass transforms clocked flip-flops to prepare a design for formal\n");
|
|
log("verification. If a design contains latches and/or multiple different clocks run\n");
|
|
log("the async2sync or clk2fflogic passes before using this pass.\n");
|
|
log("\n");
|
|
log(" -clk2ff\n");
|
|
log(" Replace all clocked flip-flops with $ff cells that use the implicit\n");
|
|
log(" global clock. This assumes, without checking, that the design uses a\n");
|
|
log(" single global clock. If that is not the case, the clk2fflogic pass\n");
|
|
log(" should be used instead.\n");
|
|
log("\n");
|
|
log(" -ff2anyinit\n");
|
|
log(" Replace uninitialized bits of $ff cells with $anyinit cells. An\n");
|
|
log(" $anyinit cell behaves exactly like an $ff cell with an undefined\n");
|
|
log(" initialization value. The difference is that $anyinit inhibits\n");
|
|
log(" don't-care optimizations and is used to track solver-provided values\n");
|
|
log(" in witness traces.\n");
|
|
log("\n");
|
|
log(" If combined with -clk2ff this also affects newly created $ff cells.\n");
|
|
log("\n");
|
|
log(" -anyinit2ff\n");
|
|
log(" Replaces $anyinit cells with uninitialized $ff cells. This performs the\n");
|
|
log(" reverse of -ff2anyinit and can be used, before running a backend pass\n");
|
|
log(" (or similar) that is not yet aware of $anyinit cells.\n");
|
|
log("\n");
|
|
log(" Note that after running -anyinit2ff, in general, performing don't-care\n");
|
|
log(" optimizations is not sound in a formal verification setting.\n");
|
|
log("\n");
|
|
log(" -fine\n");
|
|
log(" Emit fine-grained $_FF_ cells instead of coarse-grained $ff cells for\n");
|
|
log(" -anyinit2ff. Cannot be combined with -clk2ff or -ff2anyinit.\n");
|
|
log("\n");
|
|
log(" -setundef\n");
|
|
log(" Find FFs with undefined initialization values for which changing the\n");
|
|
log(" initialization does not change the observable behavior and initialize\n");
|
|
log(" them. For -ff2anyinit, this reduces the number of generated $anyinit\n");
|
|
log(" cells that drive wires with private names.\n");
|
|
log("\n");
|
|
log(" -hierarchy\n");
|
|
log(" Propagates the 'replaced_by_gclk' attribute set by clk2ff upwards\n");
|
|
log(" through the design hierarchy towards the toplevel inputs. This option\n");
|
|
log(" works on the whole design and ignores the selection.\n");
|
|
log("\n");
|
|
log(" -assume\n");
|
|
log(" Add assumptions that constrain wires with the 'replaced_by_gclk'\n");
|
|
log(" attribute to the value they would have before an active clock edge.\n");
|
|
log("\n");
|
|
log(" -declockgate\n");
|
|
log(" Detect clock-gating patterns and modify any FFs clocked by the gated\n");
|
|
log(" clock to use the ungated clock with the gate signal as clock enable.\n");
|
|
log(" This doesn't affect the design's behavior during FV but can enable the\n");
|
|
log(" use of formal verification methods that only support a single global\n");
|
|
log(" clock.\n");
|
|
|
|
// TODO: An option to check whether all FFs use the same clock before changing it to the global clock
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
bool flag_clk2ff = false;
|
|
bool flag_ff2anyinit = false;
|
|
bool flag_anyinit2ff = false;
|
|
bool flag_fine = false;
|
|
bool flag_setundef = false;
|
|
bool flag_hierarchy = false;
|
|
bool flag_assume = false;
|
|
bool flag_declockgate = false;
|
|
|
|
log_header(design, "Executing FORMALFF pass.\n");
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
if (args[argidx] == "-clk2ff") {
|
|
flag_clk2ff = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-ff2anyinit") {
|
|
flag_ff2anyinit = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-anyinit2ff") {
|
|
flag_anyinit2ff = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-fine") {
|
|
flag_fine = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-setundef") {
|
|
flag_setundef = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-hierarchy") {
|
|
flag_hierarchy = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-assume") {
|
|
flag_assume = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-declockgate") {
|
|
flag_declockgate = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
if (!(flag_clk2ff || flag_ff2anyinit || flag_anyinit2ff || flag_hierarchy || flag_assume || flag_declockgate))
|
|
log_cmd_error("One of the options -clk2ff, -ff2anyinit, -anyinit2ff, -hierarchy or -assume must be specified.\n");
|
|
|
|
if (flag_ff2anyinit && flag_anyinit2ff)
|
|
log_cmd_error("The options -ff2anyinit and -anyinit2ff are exclusive.\n");
|
|
|
|
if (flag_ff2anyinit && flag_declockgate)
|
|
log_cmd_error("The options -ff2anyinit and -declockgate are exclusive.\n");
|
|
|
|
if (flag_fine && !flag_anyinit2ff)
|
|
log_cmd_error("The option -fine requries the -anyinit2ff option.\n");
|
|
|
|
if (flag_fine && flag_clk2ff)
|
|
log_cmd_error("The options -fine and -clk2ff are exclusive.\n");
|
|
|
|
if (flag_declockgate)
|
|
{
|
|
for (auto module : design->selected_modules())
|
|
{
|
|
ModWalker modwalker(design);
|
|
modwalker.setup(module);
|
|
SigMap &sigmap = modwalker.sigmap;
|
|
FfInitVals initvals(&modwalker.sigmap, module);
|
|
|
|
dict<IdString, Mem> memories;
|
|
|
|
for (auto mem : Mem::get_selected_memories(module)) {
|
|
if (!mem.packed)
|
|
continue;
|
|
memories.emplace(mem.cell->name, std::move(mem));
|
|
}
|
|
|
|
dict<pair<SigBit, bool>, vector<Cell *>> clk_bits;
|
|
pool<SigBit> input_bits;
|
|
pool<pair<SigBit, bool>> input_clk_bits;
|
|
for (auto cell : module->selected_cells()) {
|
|
if (cell->is_builtin_ff()) {
|
|
FfData ff(&initvals, cell);
|
|
if (!ff.has_clk)
|
|
continue;
|
|
SigBit clk = sigmap(ff.sig_clk);
|
|
clk_bits[{clk, ff.pol_clk}].push_back(cell);
|
|
} else if (cell->type == ID($mem_v2)) {
|
|
auto const &mem = memories.at(cell->name);
|
|
for (auto &rd_port : mem.rd_ports)
|
|
if (rd_port.clk_enable)
|
|
clk_bits[{rd_port.clk, rd_port.clk_polarity}].push_back(mem.cell);
|
|
for (auto &wr_port : mem.wr_ports)
|
|
if (wr_port.clk_enable)
|
|
clk_bits[{wr_port.clk, wr_port.clk_polarity}].push_back(mem.cell);
|
|
}
|
|
// XXX $check $print
|
|
}
|
|
|
|
log_debug("%s has %d clk bits\n", log_id(module), GetSize(clk_bits));
|
|
|
|
for (auto port : module->ports) {
|
|
Wire *wire = module->wire(port);
|
|
if (!wire->port_input)
|
|
continue;
|
|
for (auto bit : SigSpec(wire)) {
|
|
input_bits.insert(bit);
|
|
for (bool pol : {false, true}) {
|
|
if (clk_bits.count({bit, pol})) {
|
|
input_clk_bits.insert({bit, pol});
|
|
clk_bits.erase({bit, pol});
|
|
}
|
|
}
|
|
}
|
|
}
|
|
log_debug("%s has %d non-input clk bits\n", log_id(module), GetSize(clk_bits));
|
|
|
|
if (clk_bits.empty())
|
|
continue;
|
|
|
|
for (auto &clk_bit : clk_bits)
|
|
{
|
|
SigBit clk = clk_bit.first.first;
|
|
bool pol_clk = clk_bit.first.second;
|
|
vector<Cell *> &clocked_cells = clk_bit.second;
|
|
|
|
if (!clk.is_wire()) {
|
|
log_debug("constant clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
|
|
continue;
|
|
}
|
|
if (input_bits.count(clk)) {
|
|
log_debug("input clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
|
|
continue;
|
|
}
|
|
auto found = modwalker.signal_drivers.find(clk);
|
|
if (found == modwalker.signal_drivers.end() || found->second.empty()) {
|
|
log_debug("undriven clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
|
|
continue;
|
|
}
|
|
|
|
if (found->second.size() > 1) {
|
|
log_debug("multiple drivers for clk bit %s.%s\n", log_id(module), log_signal(SigSpec(clk)));
|
|
continue;
|
|
}
|
|
|
|
auto driver = *found->second.begin();
|
|
|
|
bool is_gate =
|
|
pol_clk ? driver.cell->type.in(ID($and), ID($_AND_)) : driver.cell->type.in(ID($or), ID($_OR_));
|
|
|
|
if (!is_gate) {
|
|
log_debug("unsupported gating logic %s.%s (%s) for clock %s %s.%s\n", log_id(module),
|
|
log_id(driver.cell), log_id(driver.cell->type), pol_clk ? "posedge" : "negedge",
|
|
log_id(module), log_signal(SigSpec(clk)));
|
|
|
|
continue;
|
|
}
|
|
SigBit gate_clock = sigmap(driver.cell->getPort(ID::A)[driver.offset]);
|
|
SigBit gate_enable = sigmap(driver.cell->getPort(ID::B)[driver.offset]);
|
|
|
|
std::swap(gate_clock, gate_enable);
|
|
for (int i = 0; i < 2; i++) {
|
|
std::swap(gate_clock, gate_enable);
|
|
|
|
log_debug("clock %s.%s for gated clk bit %s.%s\n", log_id(module), log_signal(SigSpec(gate_clock)),
|
|
log_id(module), log_signal(SigSpec(clk)));
|
|
log_debug("enable %s.%s for gated clk bit %s.%s\n", log_id(module), log_signal(SigSpec(gate_enable)),
|
|
log_id(module), log_signal(SigSpec(clk)));
|
|
|
|
found = modwalker.signal_drivers.find(gate_enable);
|
|
if (found == modwalker.signal_drivers.end() || found->second.empty()) {
|
|
log_debug("undriven gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
|
|
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
|
|
continue;
|
|
}
|
|
if (found->second.size() > 1) {
|
|
log_debug("multiple drivers for gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
|
|
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
|
|
continue;
|
|
}
|
|
|
|
auto gate_driver = *found->second.begin();
|
|
|
|
if (!gate_driver.cell->is_builtin_ff()) {
|
|
log_debug("non FF driver for gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
|
|
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
|
|
continue;
|
|
}
|
|
|
|
FfData ff(&initvals, gate_driver.cell);
|
|
if (ff.has_gclk || ff.has_ce || ff.has_sr || ff.has_srst || ff.has_arst || (ff.has_aload && ff.has_clk)) {
|
|
log_debug(
|
|
"FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible type: %s\n",
|
|
log_id(module), log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)),
|
|
log_id(gate_driver.cell->type));
|
|
continue;
|
|
}
|
|
|
|
if (ff.has_aload) {
|
|
// this ff is intentionally not emitted!
|
|
ff.has_aload = false;
|
|
ff.has_clk = true;
|
|
ff.pol_clk = !ff.pol_arst;
|
|
ff.sig_clk = ff.sig_aload;
|
|
ff.sig_d = ff.sig_ad;
|
|
}
|
|
|
|
if (!ff.has_clk || sigmap(ff.sig_clk) != gate_clock || ff.pol_clk != pol_clk) {
|
|
log_debug("FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible clocking: "
|
|
"%s %s.%s\n",
|
|
log_id(module), log_signal(SigSpec(gate_enable)), log_id(module),
|
|
log_signal(SigSpec(clk)), ff.pol_clk ? "posedge" : "negedge", log_id(module),
|
|
log_signal(SigSpec(ff.sig_clk)));
|
|
continue;
|
|
}
|
|
|
|
SigBit sig_gate = ff.sig_d[gate_driver.offset];
|
|
|
|
log_debug("found clock gate, rewriting %d cells\n", GetSize(clocked_cells));
|
|
|
|
for (auto clocked_cell : clocked_cells) {
|
|
log_debug("rewriting cell %s.%s (%s)\n", log_id(module), log_id(clocked_cell),
|
|
log_id(clocked_cell->type));
|
|
|
|
if (clocked_cell->is_builtin_ff()) {
|
|
|
|
FfData ff(&initvals, clocked_cell);
|
|
log_assert(ff.has_clk);
|
|
ff.unmap_ce();
|
|
ff.pol_ce = pol_clk;
|
|
ff.sig_ce = sig_gate;
|
|
ff.has_ce = true;
|
|
ff.sig_clk = gate_clock;
|
|
ff.emit();
|
|
} else if (clocked_cell->type == ID($mem_v2)) {
|
|
auto &mem = memories.at(clocked_cell->name);
|
|
bool changed = false;
|
|
for (auto &rd_port : mem.rd_ports) {
|
|
if (rd_port.clk_enable && rd_port.clk == clk && rd_port.clk_polarity == pol_clk) {
|
|
log_debug("patching rd port\n");
|
|
changed = true;
|
|
rd_port.clk = gate_clock;
|
|
SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_ID, sig_gate));
|
|
SigSpec en_mask = SigSpec(en_bit, GetSize(rd_port.en));
|
|
rd_port.en = module->And(NEW_ID, rd_port.en, en_mask);
|
|
}
|
|
}
|
|
for (auto &wr_port : mem.wr_ports) {
|
|
if (wr_port.clk_enable && wr_port.clk == clk && wr_port.clk_polarity == pol_clk) {
|
|
log_debug("patching wr port\n");
|
|
changed = true;
|
|
wr_port.clk = gate_clock;
|
|
SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_ID, sig_gate));
|
|
SigSpec en_mask = SigSpec(en_bit, GetSize(wr_port.en));
|
|
wr_port.en = module->And(NEW_ID, wr_port.en, en_mask);
|
|
}
|
|
}
|
|
if (changed)
|
|
mem.emit();
|
|
}
|
|
}
|
|
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
for (auto module : design->selected_modules())
|
|
{
|
|
if (flag_setundef)
|
|
{
|
|
InitValWorker worker(module);
|
|
|
|
for (auto cell : module->selected_cells())
|
|
{
|
|
if (cell->is_builtin_ff())
|
|
{
|
|
FfData ff(&worker.initvals, cell);
|
|
if (ff.has_aload || ff.has_sr || ff.has_arst || ff.val_init.is_fully_def())
|
|
continue;
|
|
|
|
if (ff.has_ce && // CE can make the initval stick around
|
|
worker.initconst(ff.sig_ce.as_bit()) != (ff.pol_ce ? State::S1 : State::S0) && // unless it's known active
|
|
(!ff.has_srst || ff.ce_over_srst ||
|
|
worker.initconst(ff.sig_srst.as_bit()) != (ff.pol_srst ? State::S1 : State::S0))) // or a srst with priority is known active
|
|
continue;
|
|
|
|
auto before = ff.val_init;
|
|
for (int i = 0; i < ff.width; i++)
|
|
if (ff.val_init[i] == State::Sx && !worker.is_initval_used(ff.sig_q[i]))
|
|
ff.val_init.set(i, State::S0);
|
|
|
|
if (ff.val_init != before) {
|
|
log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",
|
|
log_id(module), log_id(cell), log_id(cell->type),
|
|
log_const(before), log_const(ff.val_init));
|
|
worker.initvals.set_init(ff.sig_q, ff.val_init);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
SigMap sigmap(module);
|
|
FfInitVals initvals(&sigmap, module);
|
|
|
|
|
|
for (auto cell : module->selected_cells())
|
|
{
|
|
if (flag_anyinit2ff && cell->type == ID($anyinit))
|
|
{
|
|
FfData ff(&initvals, cell);
|
|
ff.remove();
|
|
ff.is_anyinit = false;
|
|
ff.is_fine = flag_fine;
|
|
if (flag_fine)
|
|
for (int i = 0; i < ff.width; i++)
|
|
ff.slice({i}).emit();
|
|
else
|
|
ff.emit();
|
|
|
|
continue;
|
|
}
|
|
|
|
if (!cell->is_builtin_ff())
|
|
continue;
|
|
|
|
FfData ff(&initvals, cell);
|
|
bool emit = false;
|
|
|
|
if (flag_clk2ff && ff.has_clk) {
|
|
if (ff.sig_clk.is_fully_const())
|
|
log_error("Const CLK on %s (%s) from module %s, run async2sync first.\n",
|
|
log_id(cell), log_id(cell->type), log_id(module));
|
|
if (ff.has_aload || ff.has_arst || ff.has_sr)
|
|
log_error("Async inputs on %s (%s) from module %s, run async2sync first.\n",
|
|
log_id(cell), log_id(cell->type), log_id(module));
|
|
|
|
auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr;
|
|
|
|
if (clk_wire == nullptr) {
|
|
clk_wire = module->addWire(NEW_ID);
|
|
module->connect(RTLIL::SigBit(clk_wire), ff.sig_clk);
|
|
}
|
|
|
|
auto clk_polarity = ff.pol_clk ? State::S1 : State::S0;
|
|
|
|
std::string attribute = clk_wire->get_string_attribute(ID::replaced_by_gclk);
|
|
|
|
auto &attr = clk_wire->attributes[ID::replaced_by_gclk];
|
|
|
|
if (!attr.empty() && attr != clk_polarity)
|
|
log_error("CLK %s on %s (%s) from module %s also used with opposite polarity, run clk2fflogic instead.\n",
|
|
log_id(clk_wire), log_id(cell), log_id(cell->type), log_id(module));
|
|
|
|
attr = clk_polarity;
|
|
clk_wire->set_bool_attribute(ID::keep);
|
|
|
|
// TODO propagate the replaced_by_gclk attribute upwards throughout the hierarchy
|
|
|
|
ff.unmap_ce_srst();
|
|
ff.has_clk = false;
|
|
ff.has_gclk = true;
|
|
emit = true;
|
|
}
|
|
|
|
if (!ff.has_gclk) {
|
|
continue;
|
|
}
|
|
|
|
if (flag_ff2anyinit && !ff.val_init.is_fully_def())
|
|
{
|
|
ff.remove();
|
|
emit = false;
|
|
|
|
int cursor = 0;
|
|
while (cursor < ff.val_init.size())
|
|
{
|
|
bool is_anyinit = ff.val_init[cursor] == State::Sx;
|
|
std::vector<int> bits;
|
|
bits.push_back(cursor++);
|
|
while (cursor < ff.val_init.size() && (ff.val_init[cursor] == State::Sx) == is_anyinit)
|
|
bits.push_back(cursor++);
|
|
|
|
if ((int)bits.size() == ff.val_init.size()) {
|
|
// This check is only to make the private names more helpful for debugging
|
|
ff.is_anyinit = true;
|
|
ff.is_fine = false;
|
|
emit = true;
|
|
break;
|
|
}
|
|
|
|
auto slice = ff.slice(bits);
|
|
slice.is_anyinit = is_anyinit;
|
|
slice.is_fine = false;
|
|
slice.emit();
|
|
}
|
|
}
|
|
|
|
if (emit)
|
|
ff.emit();
|
|
}
|
|
}
|
|
|
|
if (flag_hierarchy) {
|
|
HierarchyWorker worker(design);
|
|
worker.propagate();
|
|
}
|
|
|
|
if (flag_assume) {
|
|
for (auto module : design->selected_modules()) {
|
|
std::vector<pair<SigBit, bool>> found;
|
|
for (auto wire : module->wires()) {
|
|
if (!wire->has_attribute(ID::replaced_by_gclk))
|
|
continue;
|
|
bool clk_pol = wire->attributes[ID::replaced_by_gclk].at(0) == State::S1;
|
|
|
|
found.emplace_back(SigSpec(wire), clk_pol);
|
|
}
|
|
for (auto pair : found) {
|
|
SigBit clk = pair.first;
|
|
|
|
if (pair.second)
|
|
clk = module->Not(NEW_ID, clk);
|
|
|
|
module->addAssume(NEW_ID, clk, State::S1);
|
|
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} FormalFfPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|