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59 lines
1.1 KiB
Text
59 lines
1.1 KiB
Text
# ABC synthesis comparison: with vs without csa_tree
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# Baseline: no csa_tree
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read_verilog abc_bench_add8.v
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hierarchy -top abc_bench_add8
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proc; opt
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techmap
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abc -g AND,OR,XOR
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opt_clean
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stat
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# Baseline is typically 238 gates — assert it's above 235
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select -assert-min 236 t:$_AND_ t:$_OR_ t:$_XOR_ %u
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design -reset
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# With csa_tree
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read_verilog abc_bench_add8.v
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hierarchy -top abc_bench_add8
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proc; opt
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csa_tree
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techmap
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abc -g AND,OR,XOR
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opt_clean
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stat
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# CSA was giving ~232 gates, assert rough equality
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select -assert-max 235 t:$_AND_ t:$_OR_ t:$_XOR_ %u
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design -reset
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# Depth-optimal: baseline
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read_verilog abc_bench_add8.v
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hierarchy -top abc_bench_add8
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proc; opt
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techmap
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abc -D 1
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opt_clean
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stat
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# Baseline depth-optimal is ~243 cells
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select -assert-min 240 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u
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design -reset
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# Depth-optimal: with csa_tree
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read_verilog abc_bench_add8.v
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hierarchy -top abc_bench_add8
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proc; opt
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csa_tree
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techmap
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abc -D 1
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opt_clean
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stat
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# CSA depth-optimal is ~232 cells, must be under baseline
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select -assert-max 236 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u
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log "CSA depth and gate count: ok"
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