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yosys/techlibs/ice40
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gatecat cae905f551 Blackbox all whiteboxes after synthesis 
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
..
tests
.gitignore
abc9_model.v
arith_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
brams.txt
brams_init.py
brams_map.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
cells_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cells_sim.v Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH 2020-06-14 00:45:22 -07:00
dsp_map.v
ff_map.v ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
ice40_braminit.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
ice40_opt.cc synth_ice40: Use opt_dff. 2020-07-30 22:26:20 +02:00
latches_map.v
Makefile.inc synth_ice40: Use opt_dff. 2020-07-30 22:26:20 +02:00
synth_ice40.cc Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00