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https://github.com/YosysHQ/yosys
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4bee908ae8
* enable mixed read-width / write-width ports in SDP mode * fix NO_CHANGE and WRITE_THROUGH behavior during read access * remove redundant zero-initialization * set A/B_WE bit during map (gatemate_bramopt pass could be removed later) * differentiate "upper" and "lower" initialization for cascade mode |
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| .. | ||
| arith_map.v | ||
| brams.txt | ||
| brams_init_20.vh | ||
| brams_init_40.vh | ||
| brams_map.v | ||
| cells_bb.v | ||
| cells_sim.v | ||
| gatemate_bramopt.cc | ||
| iob_map.v | ||
| lut_map.v | ||
| Makefile.inc | ||
| mul_map.v | ||
| mux_map.v | ||
| reg_map.v | ||
| synth_gatemate.cc | ||