3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
yosys/techlibs/gatemate
Patrick Urban 4bee908ae8 synth_gatemate: Revise block RAM read modes and initialization
* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode
2021-11-13 21:53:25 +01:00
..
arith_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams.txt synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams_init_20.vh synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams_init_40.vh synth_gatemate: Revise block RAM read modes and initialization 2021-11-13 21:53:25 +01:00
brams_map.v synth_gatemate: Revise block RAM read modes and initialization 2021-11-13 21:53:25 +01:00
cells_bb.v synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
cells_sim.v synth_gatemate: Revise block RAM read modes and initialization 2021-11-13 21:53:25 +01:00
gatemate_bramopt.cc synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
iob_map.v synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
lut_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
Makefile.inc synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
mul_map.v synth_gatemate: Rename multiplier factor parameters 2021-11-13 21:53:25 +01:00
mux_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
reg_map.v synth_gatemate: Remove unsupported FF initialization 2021-11-13 21:53:25 +01:00
synth_gatemate.cc synth_gatemate: Registers are uninitialized 2021-11-13 21:53:25 +01:00