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yosys/techlibs/gatemate
Miodrag Milanović febc07e6fb
Merge pull request #5039 from YosysHQ/gatemate_bram
gatemate: WRITE_THROUGH mode change
2025-04-25 09:53:43 +02:00
..
.gitignore
arith_map.v
brams.txt gatemate: WRITE_THROUGH mode change 2025-04-18 14:16:02 +02:00
brams_init_20.vh
brams_init_40.vh
brams_map.v
cells_bb.v gatemate: Add CC_SERDES parameters and update port names 2025-01-10 10:25:10 +01:00
cells_sim.v Change to blocking assignments in non-clocked process. 2025-04-23 17:13:37 +02:00
gatemate_foldinv.cc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
inv_map.v
lut_map.v
make_lut_tree_lib.py
Makefile.inc
mul_map.v
mux_map.v
reg_map.v
synth_gatemate.cc gatemate: run simplemap after muxcover to prevent unmapped multiplexers 2024-11-15 09:49:49 +01:00