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24 lines
466 B
Text
24 lines
466 B
Text
read_verilog <<EOT
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module top #(
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parameter integer WIDTH = 12
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)(
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output reg [WIDTH:0] cnt,
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input wire clk,
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input wire rst
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);
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wire last_n;
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assign last_n = cnt[WIDTH];
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always @(posedge clk or posedge rst)
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if (rst)
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cnt <= 0;
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else
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cnt <= last_n ? ( cnt + { (WIDTH+1){last_n} } ) : 13'h1aaa;
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endmodule
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EOT
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synth_ice40
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splitnets
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select -assert-count 12 t:SB_CARRY %co:+[CO] t:SB_LUT4 %ci:+[I3] %i
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