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17 lines
422 B
Systemverilog
17 lines
422 B
Systemverilog
function [9728-1:0] rf_init_to_string;
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input [1152-1:0] array;
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input integer blocks;
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input integer width;
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reg [9728-1:0] temp; // (1152+1152/18)*8
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integer i;
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begin
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temp = "";
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for (i = 0; i < blocks; i = i + 1) begin
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if (i != 0) begin
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temp = {temp, ","};
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end
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temp = {temp, $sformatf("%b",array[(i+1)*width-1: i*width])};
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end
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rf_init_to_string = temp;
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end
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endfunction
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