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https://github.com/YosysHQ/yosys
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136 lines
2.9 KiB
Verilog
136 lines
2.9 KiB
Verilog
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//Cells still in this file have INCOMPLETE simulation models, need to finish them
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module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
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parameter PWRDN_SYNC = 1'b0;
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parameter CLK_EDGE = "RISING";
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parameter GREATER_OR_EQUAL = 1'b0;
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//TODO implement power-down mode
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initial GREATER = 0;
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initial EQUAL = 0;
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wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
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always @(posedge clk_minv) begin
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if(GREATER_OR_EQUAL)
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GREATER <= (INP >= INN);
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else
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GREATER <= (INP > INN);
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EQUAL <= (INP == INN);
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end
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endmodule
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module GP_EDGEDET(input IN, output reg OUT);
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parameter EDGE_DIRECTION = "RISING";
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parameter DELAY_STEPS = 1;
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parameter GLITCH_FILTER = 0;
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//not implemented for simulation
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endmodule
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module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter HARDIP_DIV = 1;
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parameter FABRIC_DIV = 1;
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parameter OSC_FREQ = "25k";
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initial CLKOUT_HARDIP = 0;
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initial CLKOUT_FABRIC = 0;
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//output dividers not implemented for simulation
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//auto powerdown not implemented for simulation
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always begin
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if(PWRDN) begin
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CLKOUT_HARDIP = 0;
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CLKOUT_FABRIC = 0;
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end
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else begin
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if(OSC_FREQ == "25k") begin
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//half period of 25 kHz
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#20000;
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end
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else begin
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//half period of 2 MHz
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#250;
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end
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CLKOUT_HARDIP = ~CLKOUT_HARDIP;
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CLKOUT_FABRIC = ~CLKOUT_FABRIC;
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end
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end
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endmodule
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module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter HARDIP_DIV = 1;
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parameter FABRIC_DIV = 1;
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initial CLKOUT_HARDIP = 0;
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initial CLKOUT_FABRIC = 0;
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//output dividers not implemented for simulation
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//auto powerdown not implemented for simulation
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always begin
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if(PWRDN) begin
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CLKOUT_HARDIP = 0;
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CLKOUT_FABRIC = 0;
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end
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else begin
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//half period of 27 MHz
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#18.518;
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CLKOUT_HARDIP = ~CLKOUT_HARDIP;
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CLKOUT_FABRIC = ~CLKOUT_FABRIC;
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end
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end
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endmodule
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module GP_SPI(
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input SCK,
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inout SDAT,
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input CSN,
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input[7:0] TXD_HIGH,
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input[7:0] TXD_LOW,
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output reg[7:0] RXD_HIGH,
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output reg[7:0] RXD_LOW,
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output reg INT);
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initial RXD_HIGH = 0;
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initial RXD_LOW = 0;
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initial INT = 0;
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parameter DATA_WIDTH = 8; //byte or word width
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parameter SPI_CPHA = 0; //SPI clock phase
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parameter SPI_CPOL = 0; //SPI clock polarity
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parameter DIRECTION = "INPUT"; //SPI data direction (either input to chip or output to host)
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//parallel output to fabric not yet implemented
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//TODO: write sim model
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//TODO: SPI SDIO control... can we use ADC output while SPI is input??
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//TODO: clock sync
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endmodule
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//keep constraint needed to prevent optimization since we have no outputs
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(* keep *)
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module GP_SYSRESET(input RST);
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parameter RESET_MODE = "EDGE";
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parameter EDGE_SPEED = 4;
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//cannot simulate whole system reset
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endmodule
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