mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
336 lines
9.6 KiB
C++
336 lines
9.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthGowinPass : public ScriptPass
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{
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SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_gowin [options]\n");
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log("\n");
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log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -vout <file>\n");
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log(" write the design to the specified Verilog netlist file. writing of an\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON netlist file. writing of an\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log(" This disables features not yet supported by nexpnr-gowin.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -nodffe\n");
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log(" do not use flipflops with CE in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use BRAM cells in output netlist\n");
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log("\n");
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log(" -nolutram\n");
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log(" do not use distributed RAM cells in output netlist\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log(" -nowidelut\n");
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log(" do not use muxes to implement LUTs larger than LUT4s\n");
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log("\n");
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log(" -noiopads\n");
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log(" do not emit IOB at top level ports\n");
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log("\n");
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log(" -noalu\n");
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log(" do not use ALU cells\n");
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log("\n");
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log(" -noabc9\n");
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log(" disable use of new ABC9 flow\n");
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log("\n");
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log(" -no-rw-check\n");
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log(" marks all recognized read ports as \"return don't-care value on\n");
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log(" read/write collision\" (same result as setting the no_rw_check\n");
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log(" attribute on all memories).\n");
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log("\n");
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log(" -family <family>\n");
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log(" sets the gowin family to the specified value. The default is 'gw1n'.\n");
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log(" The following families are supported:\n");
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log(" 'gw1n', 'gw2a', 'gw5a'.\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, vout_file, json_file, family;
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bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads, noalu, no_rw_check;
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void clear_flags() override
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{
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family = "gw1n";
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top_opt = "-auto-top";
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vout_file = "";
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json_file = "";
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retime = false;
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flatten = true;
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nobram = false;
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nodffe = false;
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nolutram = false;
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nowidelut = false;
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abc9 = true;
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noiopads = false;
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noalu = false;
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no_rw_check = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-vout" && argidx+1 < args.size()) {
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vout_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-family" && argidx+1 < args.size()) {
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family = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-nolutram" || /*deprecated*/args[argidx] == "-nodram") {
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nolutram = true;
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continue;
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}
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if (args[argidx] == "-nodffe") {
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nodffe = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-nowidelut") {
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nowidelut = true;
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continue;
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}
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if (args[argidx] == "-noalu") {
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noalu = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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// removed, ABC9 is on by default.
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continue;
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}
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if (args[argidx] == "-noabc9") {
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abc9 = false;
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continue;
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}
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if (args[argidx] == "-noiopads") {
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noiopads = true;
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continue;
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}
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if (args[argidx] == "-no-rw-check") {
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no_rw_check = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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log_header(design, "Executing SYNTH_GOWIN pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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std::string no_rw_check_opt = "";
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if (no_rw_check)
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no_rw_check_opt = " -no-rw-check";
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if (help_mode)
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no_rw_check_opt = " [-no-rw-check]";
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if (check_label("begin"))
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{
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run("read_verilog -specify -lib +/gowin/cells_sim.v");
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run(stringf("read_verilog -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "<family>" : family));
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
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}
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if (flatten && check_label("flatten", "(unless -noflatten)"))
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{
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run("proc");
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run("flatten");
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run("tribuf -logic");
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run("deminout");
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}
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if (check_label("coarse"))
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{
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run("synth -run coarse" + no_rw_check_opt);
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}
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if (check_label("map_ram"))
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{
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std::string args = "";
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if (help_mode)
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args += " [-no-auto-block] [-no-auto-distributed]";
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else {
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if (nobram)
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args += " -no-auto-block";
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if (nolutram)
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args += " -no-auto-distributed";
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}
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run("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
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run("techmap -map +/gowin/lutrams_map.v -map +/gowin/brams_map.v");
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}
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if (check_label("map_ffram"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map");
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run("opt -undriven -fine");
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}
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if (check_label("map_gates"))
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{
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if (noalu) {
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run("techmap -map +/techmap.v");
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} else {
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run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
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}
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run("opt -fast");
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if (retime || help_mode)
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run("abc -dff -D 1", "(only if -retime)");
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if (!noiopads || help_mode)
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run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
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"-toutpad TBUF ~OEN:I:O -tinoutpad IOBUF ~OEN:O:I:IO", "(unless -noiopads)");
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}
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if (check_label("map_ffs"))
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{
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run("opt_clean");
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if (nodffe)
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run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFF_?P?_ r -cell $_DFF_?P?_ r");
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else
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run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r");
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run("techmap -map +/gowin/cells_map.v");
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run("opt_expr -mux_undef");
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run("simplemap");
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}
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if (check_label("map_luts"))
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{
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if (nowidelut && abc9) {
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run("read_verilog -icells -lib -specify +/abc9_model.v");
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run("abc9 -maxlut 4 -W 500");
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} else if (nowidelut && !abc9) {
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run("abc -lut 4");
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} else if (!nowidelut && abc9) {
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run("read_verilog -icells -lib -specify +/abc9_model.v");
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run("abc9 -maxlut 8 -W 500");
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} else if (!nowidelut && !abc9) {
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run("abc -lut 4:8");
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}
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run("clean");
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}
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if (check_label("map_cells"))
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{
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run("techmap -map +/gowin/cells_map.v");
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run("opt_lut_ins -tech gowin");
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run("setundef -undriven -params -zero");
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run("hilomap -singleton -hicell VCC V -locell GND G");
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if (!vout_file.empty() || help_mode) // vendor output requires 1-bit wires
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run("splitnets -ports", "(only if -vout used)");
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run("clean");
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run("autoname");
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}
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if (check_label("check"))
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{
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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run("blackbox =A:whitebox");
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}
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if (check_label("vout"))
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{
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if (!vout_file.empty() || help_mode)
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run(stringf("write_verilog -simple-lhs -decimal -attr2comment -defparam -renameprefix gen %s",
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help_mode ? "<file-name>" : vout_file.c_str()));
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s",
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help_mode ? "<file-name>" : json_file.c_str()));
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}
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}
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} SynthGowinPass;
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PRIVATE_NAMESPACE_END
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