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https://github.com/YosysHQ/yosys
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20c2708383
Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
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21 lines
466 B
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Internal flow
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=============
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A (usually short) synthesis script controls Yosys.
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This scripts contain three types of commands:
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- **Frontends**, that read input files (usually Verilog);
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- **Passes**, that perform transformations on the design in memory;
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- **Backends**, that write the design in memory to a file (various formats are
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available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).
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.. toctree::
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:maxdepth: 2
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overview
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control_and_data
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verilog_frontend
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