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38 lines
786 B
Text
38 lines
786 B
Text
read_verilog sub_mixed.v
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hierarchy -top sub_mixed
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proc; opt_clean
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csa_tree
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opt_clean
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# 10 + 20 - 5 + 3 = 28
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sat -set a 10 -set b 20 -set c 5 -set d 3 -prove y 28
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# 0 + 0 - 0 + 0 = 0
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sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
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# 100 + 50 - 30 + 10 = 130
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sat -set a 100 -set b 50 -set c 30 -set d 10 -prove y 130
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# 1 + 1 - 255 + 1 = 4
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sat -set a 1 -set b 1 -set c 255 -set d 1 -prove y 4
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log "sub_mixed vectors: ok"
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design -reset
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read_verilog sub_all.v
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hierarchy -top sub_all
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proc; opt_clean
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csa_tree
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opt_clean
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# 100 - 10 - 20 - 30 = 40
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sat -set a 100 -set b 10 -set c 20 -set d 30 -prove y 40
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# 0 - 0 - 0 - 0 = 0
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sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0
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# 255 - 1 - 1 - 1 = 252
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sat -set a 255 -set b 1 -set c 1 -set d 1 -prove y 252
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log "sub_all vectors: ok"
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