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https://github.com/YosysHQ/yosys
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54 lines
1.5 KiB
Verilog
54 lines
1.5 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Martin Povišer <povik@cutebit.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* techmap_celltype = "$lcu" *)
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module _80_lcu_kogge_stone (P, G, CI, CO);
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parameter WIDTH = 2;
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(* force_downto *)
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input [WIDTH-1:0] P, G;
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input CI;
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(* force_downto *)
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output [WIDTH-1:0] CO;
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integer i, j;
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(* force_downto *)
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reg [WIDTH-1:0] p, g;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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always @* begin
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p = P;
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g = G;
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// in almost all cases CI will be constant zero
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g[0] = g[0] | (p[0] & CI);
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for (i = 0; i < $clog2(WIDTH); i = i + 1) begin
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// iterate in reverse so we don't confuse a result from this stage and the previous
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for (j = WIDTH - 1; j >= 2**i; j = j - 1) begin
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g[j] = g[j] | p[j] & g[j - 2**i];
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p[j] = p[j] & p[j - 2**i];
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end
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end
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end
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assign CO = g;
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endmodule
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