mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
479 lines
14 KiB
C++
479 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) Martin Povišer <povik@cutebit.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Used to propagate information out of a module
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struct ModuleIndex {
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Module *module;
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SigMap sigmap;
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SigPool used;
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dict<SigBit, SigBit> constant_outputs;
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std::vector<SigSpec> tie_together_outputs;
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ModuleIndex(Module *module)
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: module(module), sigmap(module)
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{
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if (module->get_blackbox_attribute()) {
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for (auto wire : module->wires()) {
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for (auto bit : SigSpec(wire))
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used.add(sigmap(bit));
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}
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return;
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}
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auto count_usage = [&](const SigSpec &signal) {
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for (auto bit : signal)
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used.add(sigmap(bit));
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};
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for (auto wire : module->wires()) {
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if (wire->port_output) {
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SigSpec wire1 = wire;
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count_usage(wire1);
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}
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}
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for (auto [_, process] : module->processes)
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process->rewrite_sigspecs(count_usage);
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for (auto cell : module->cells()) {
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bool known = cell->known();
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for (auto &conn : cell->connections()) {
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if (!known || cell->input(conn.first))
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count_usage(conn.second);
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}
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}
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dict<SigBit, SigSpec> classes;
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for (auto &pair : module->connections_) {
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for (int i = 0; i < pair.first.size(); i++) {
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if (pair.first[i].wire
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&& pair.first[i].wire->port_output
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&& !pair.first[i].wire->port_input) {
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if (!pair.second[i].wire) {
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constant_outputs[pair.first[i]] = pair.second[i];
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} else {
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classes[pair.second[i]].append(pair.first[i]);
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}
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}
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}
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}
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for (auto [key, new_class] : classes) {
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if (new_class.size() > 1) {
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new_class.sort_and_unify();
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tie_together_outputs.push_back(new_class);
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}
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}
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}
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bool apply_changes(ModuleIndex &parent, Cell *instantiation) {
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log_assert(instantiation->module == parent.module);
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if (module->get_blackbox_attribute()) {
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// no propagating out of blackboxes
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return false;
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}
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bool changed = false;
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for (auto &[port_name, value] : instantiation->connections_) {
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Wire *port = module->wire(port_name);
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if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
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log_error("Port %s connected on instance %s not found in module %s"
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" or width is not matching\n",
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log_id(port_name), log_id(instantiation), log_id(module));
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}
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if (port->port_input && port->port_output) {
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// ignore bidirectional: hard to come up with sound handling
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continue;
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}
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int nunused = 0, nconstants = 0;
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// disconnect unused inputs
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if (port->port_input) {
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for (int i = 0; i < port->width; i++) {
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if (value[i].is_wire() && !used.check(sigmap(SigBit(port, i)))) {
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value[i] = RTLIL::Sx;
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nunused++;
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}
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}
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}
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// propagate constants
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if (port->port_output) {
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SigSpec port_new_const;
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for (int i = 0; i < port->width; i++) {
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SigBit port_bit(port, i);
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if (value[i].is_wire() && constant_outputs.count(port_bit) && parent.used.check(value[i])) {
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port_new_const.append(port_bit);
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nconstants++;
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}
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}
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for (auto chunk : port_new_const.chunks()) {
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RTLIL::SigSpec rhs = chunk;
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rhs.replace(constant_outputs);
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log_assert(rhs.is_fully_const());
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parent.module->connect(value.extract(chunk.offset, chunk.width), rhs);
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SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("const_output"), chunk.width);
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for (int i = 0; i < chunk.width; i++)
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value[chunk.offset + i] = dummy[i];
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}
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}
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if (nunused > 0) {
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log("Disconnected %d input bits of instance '%s' (type '%s') in '%s'\n",
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nunused, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
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changed = true;
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}
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if (nconstants > 0) {
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log("Substituting constant for %d output bits of instance '%s' (type '%s') in '%s'\n",
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nconstants, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
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changed = true;
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}
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}
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// propagate tie-togethers
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int ntie_togethers = 0;
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SigSpec severed_port_bits;
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for (auto class_ : tie_together_outputs) {
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// filtered class represented by bits on the two sides of boundary
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SigSpec new_tie;
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for (auto port_bit : class_) {
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if (instantiation->connections_.count(port_bit.wire->name)) {
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SigBit bit = instantiation->connections_.at(port_bit.wire->name)[port_bit.offset];
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if (parent.used.check(bit)) {
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if (!new_tie.empty()) {
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severed_port_bits.append(port_bit);
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ntie_togethers++;
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}
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new_tie.append(bit);
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}
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}
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}
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if (new_tie.size() > 1)
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parent.module->connect(new_tie.extract_end(1), SigSpec(new_tie[0]).repeat(new_tie.size() - 1));
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}
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severed_port_bits.sort_and_unify();
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for (auto chunk : severed_port_bits.chunks()) {
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SigSpec &value = instantiation->connections_.at(chunk.wire->name);
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SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("tie_together"), chunk.width);
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for (int i = 0; i < chunk.width; i++)
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value[chunk.offset + i] = dummy[i];
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}
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if (ntie_togethers > 0) {
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log("Replacing %d output bits with tie-togethers on instance '%s' of '%s' in '%s'\n",
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ntie_togethers, log_id(instantiation), log_id(instantiation->type), log_id(parent.module));
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changed = true;
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}
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return changed;
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}
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};
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// Used to propagate information into a module
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struct UsageData {
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Module *module;
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SigPool used_outputs;
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// Values are constant nets. We're not using `dict<SigBit, State>`
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// since we want to use this with `SigSpec::replace()`
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dict<SigBit, SigBit> constant_inputs;
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std::vector<SigSpec> tie_together_inputs;
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SigSpec all_inputs;
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SigSpec all_outputs;
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UsageData(Module *module)
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: module(module)
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{
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SigSpec all_inputs;
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for (auto port_name : module->ports) {
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Wire *port = module->wire(port_name);
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log_assert(port);
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if (port->port_input && port->port_output) {
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// ignore bidirectional: hard to come up with sound handling
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continue;
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}
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if (port->port_input) {
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for (int i = 0; i < port->width; i++) {
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constant_inputs[SigBit(port, i)] = RTLIL::Sx;
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}
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all_inputs.append(port);
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} else {
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all_outputs.append(port);
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}
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}
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tie_together_inputs.push_back(all_inputs);
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}
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void refine_used_outputs(Wire *port, SigSpec connection, ModuleIndex &index) {
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for (int i = 0; i < port->width; i++) {
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if (connection[i].is_wire() && index.used.check(index.sigmap(connection[i]))) {
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used_outputs.add(SigBit(port, i));
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}
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}
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}
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void refine_input_constants(Wire *port, SigSpec connection) {
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for (int i = 0; i < port->width; i++) {
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SigBit port_bit(port, i);
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// is connnected constant incompatible with candidate constant?
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if (connection[i] != RTLIL::Sx
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&& constant_inputs.count(port_bit)
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&& constant_inputs.at(port_bit) != connection[i]) {
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// we can go Sx -> S1/S0, otherwise erase the candidate constant
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if (constant_inputs.at(port_bit) == RTLIL::Sx && !connection[i].is_wire()) {
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constant_inputs[port_bit] = connection[i];
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} else {
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constant_inputs.erase(port_bit);
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}
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}
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}
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}
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void refine_tie_togethers(const dict<SigBit, SigBit> &inputs) {
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std::vector<SigSpec> new_tie_togethers;
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for (auto &class_ : tie_together_inputs) {
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dict<SigBit, SigSpec> new_classes;
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for (auto bit : class_) {
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SigBit connected_bit = inputs.count(bit) ? inputs.at(bit) : RTLIL::Sx;
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new_classes[connected_bit].append(bit);
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}
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for (auto [key, new_class] : new_classes) {
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if (new_class.size() > 1)
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new_tie_togethers.push_back(new_class);
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}
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}
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new_tie_togethers.swap(tie_together_inputs);
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}
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// inspect the given instantiation and refine usage data accordingly
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void refine(Cell *instance, ModuleIndex &index) {
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dict<SigBit, SigBit> inputs;
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for (auto &[port_name, value] : instance->connections_) {
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Wire *port = module->wire(port_name);
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if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) {
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log_error("Port %s connected on instance %s not found in module %s"
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" or width is not matching\n",
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log_id(port_name), log_id(instance), log_id(module));
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}
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if (port->port_input && port->port_output) {
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// ignore bidirectional: hard to come up with sound handling
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continue;
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}
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if (port->port_output) {
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refine_used_outputs(port, value, index);
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} else {
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refine_input_constants(port, value);
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for (int i = 0; i < port->width; i++)
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inputs[SigBit(port, i)] = value[i];
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}
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}
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refine_tie_togethers(inputs);
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}
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bool apply_changes(ModuleIndex &index) {
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bool did_something = false;
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if (module->get_blackbox_attribute()) {
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// no propagating into blackboxes
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return false;
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}
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// Disconnect unused outputs
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for (auto &pair : module->connections_) {
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for (int i = 0; i < pair.first.size(); i++) {
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// If an output is constant there's no benefit to disconnecting
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// so consider it "used"
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if (pair.first[i].wire
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&& pair.first[i].wire->port_output
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&& !pair.second[i].wire)
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used_outputs.add(pair.first[i]);
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}
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}
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SigSpec disconnect_outputs;
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for (auto bit : all_outputs) {
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if (!used_outputs.check(bit))
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disconnect_outputs.append(bit);
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}
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dict<SigBit, SigBit> replacement_map;
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for (auto chunk : disconnect_outputs.chunks()) {
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Wire *repl_wire = module->addWire(module->uniquify(std::string("$") + chunk.wire->name.str()), chunk.size());
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for (int i = 0; i < repl_wire->width; i++)
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replacement_map[SigSpec(chunk)[i]] = SigBit(repl_wire, i);
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}
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auto disconnect_rewrite = [&](SigSpec &signal) {
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signal.replace(replacement_map);
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};
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module->rewrite_sigspecs(disconnect_rewrite);
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for (auto chunk : disconnect_outputs.chunks()) {
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log("Disconnected unused output terminal '%s' in module '%s'\n", log_signal(chunk), log_id(module));
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did_something = true;
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module->connect(chunk, SigSpec(RTLIL::Sx, chunk.size()));
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}
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// Connect constant inputs
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SigPool applied_constants;
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auto constant_rewrite = [&](SigSpec &signal) {
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for (auto bit : signal) {
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if (constant_inputs.count(bit))
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applied_constants.add(bit);
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}
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signal.replace(constant_inputs);
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};
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module->rewrite_sigspecs(constant_rewrite);
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SigSpec applied_constants2 = applied_constants.export_all();
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applied_constants2.sort_and_unify();
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for (auto chunk : applied_constants2.chunks()) {
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SigSpec const_ = chunk;
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const_.replace(constant_inputs);
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log("Substituting constant %s for input terminal '%s' in module '%s'\n",
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log_signal(const_), log_signal(chunk), log_id(module));
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}
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// Propagate tied-together inputs
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dict<SigBit, SigBit> ties;
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for (auto group : tie_together_inputs) {
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// Only consider used inputs for a tie-together group.
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// ModuleIndex::apply_changes might have disconnected
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// unused inputs.
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SigSpec filtered_group;
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for (auto bit : group) {
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if (index.used.check(bit))
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filtered_group.append(bit);
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}
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for (int i = 1; i < filtered_group.size(); i++)
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ties[filtered_group[i]] = filtered_group[0];
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}
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SigPool applied_ties;
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auto ties_rewrite = [&](SigSpec &signal) {
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for (auto bit : signal) {
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if (ties.count(bit)) {
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applied_ties.add(bit);
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}
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}
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signal.replace(ties);
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};
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module->rewrite_sigspecs(ties_rewrite);
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if (applied_ties.size()) {
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log("Replacing %zu input terminal bits with tie-togethers in module '%s'\n",
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applied_ties.size(), log_id(module));
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}
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return did_something;
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}
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};
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struct OptHierPass : Pass {
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OptHierPass() : Pass("opt_hier", "perform cross-boundary optimization") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_hier [selection]\n");
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log("\n");
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log("This pass considers the design hierarchy and propagates unused signals, constant\n");
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log("signals, and tied-together signals across module boundaries to facilitate\n");
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log("optimization. Only the selected modules are affected.\n");
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log("\n");
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log("Note this pass changes port semantics on modules which are not the top.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *d) override
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{
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log_header(d, "Executing OPT_HIER pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, d);
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if (!d->top_module())
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log_cmd_error("Top module needs to be selected for opt_hier\n");
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dict<IdString, ModuleIndex> indices;
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for (auto module : d->modules()) {
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log_debug("Building index for %s\n", log_id(module));
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indices.emplace(module->name, ModuleIndex(module));
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}
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dict<IdString, UsageData> usage_datas;
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for (auto module : d->selected_modules(RTLIL::SELECT_WHOLE_ONLY, RTLIL::SB_UNBOXED_CMDERR)) {
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if (module->get_bool_attribute(ID::top))
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continue;
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log_debug("Starting usage data for %s\n", log_id(module));
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usage_datas.emplace(module->name, UsageData(module));
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}
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for (auto module : d->modules()) {
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for (auto cell : module->cells()) {
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if (usage_datas.count(cell->type)) {
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log_debug("Account for instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module));
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usage_datas.at(cell->type).refine(cell, indices.at(module->name));
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}
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}
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}
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bool did_something = false;
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for (auto module : d->selected_modules(RTLIL::SELECT_WHOLE_ONLY, RTLIL::SB_UNBOXED_CMDERR)) {
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ModuleIndex &parent_index = indices.at(module->name);
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if (usage_datas.count(module->name)) {
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log_debug("Applying usage data changes to %s\n", log_id(module));
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did_something |= usage_datas.at(module->name).apply_changes(parent_index);
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}
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for (auto cell : module->cells()) {
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if (indices.count(cell->type)) {
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log_debug("Applying changes to instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module));
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did_something |= indices.at(cell->type).apply_changes(parent_index, cell);
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}
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}
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}
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if (did_something)
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d->scratchpad_set_bool("opt.did_something", true);
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}
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} OptHierPass;
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PRIVATE_NAMESPACE_END
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