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40 lines
598 B
Verilog
40 lines
598 B
Verilog
module alu(
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input clk,
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input [7:0] A,
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input [7:0] B,
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input [3:0] operation,
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output reg [7:0] result,
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output reg CF,
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output reg ZF,
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output reg SF
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);
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localparam ALU_OP_ADD = 4'b0000;
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localparam ALU_OP_SUB = 4'b0001;
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reg [8:0] tmp;
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always @(posedge clk)
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begin
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case (operation)
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ALU_OP_ADD :
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tmp = A + B;
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ALU_OP_SUB :
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tmp = A - B;
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endcase
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CF <= tmp[8];
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ZF <= tmp[7:0] == 0;
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SF <= tmp[7];
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result <= tmp[7:0];
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end
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endmodule
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module foo(
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input [7:0] a, input [7:0] b, output [7:0] y
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);
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wire [7:0] bb;
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assign b = bb;
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assign y = a + bb;
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endmodule
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