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https://github.com/YosysHQ/yosys
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72787f52fc
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
112 lines
3.4 KiB
C++
112 lines
3.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static SigSpec or_generator(Module *module, const SigSpec &sig)
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{
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switch (GetSize(sig))
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{
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case 0:
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return State::S0;
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case 1:
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return sig;
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case 2:
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return module->Or(NEW_ID, sig[0], sig[1]);
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default:
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return module->ReduceOr(NEW_ID, sig);
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}
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}
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static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data, const SigSpec &sig_sel, SigSpec &sig_or)
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{
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if (GetSize(sig_sel) == 1) {
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sig_or.append(sig_sel);
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return sig_data;
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}
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int left_size = GetSize(sig_sel) / 2;
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int right_size = GetSize(sig_sel) - left_size;
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int stride = GetSize(sig_data) / GetSize(sig_sel);
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SigSpec left_data = sig_data.extract(0, stride*left_size);
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SigSpec right_data = sig_data.extract(stride*left_size, stride*right_size);
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SigSpec left_sel = sig_sel.extract(0, left_size);
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SigSpec right_sel = sig_sel.extract(left_size, right_size);
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SigSpec left_or, left_result, right_result;
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left_result = recursive_mux_generator(module, left_data, left_sel, left_or);
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right_result = recursive_mux_generator(module, right_data, right_sel, sig_or);
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left_or = or_generator(module, left_or);
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sig_or.append(left_or);
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return module->Mux(NEW_ID, right_result, left_result, left_or);
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}
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struct PmuxtreePass : public Pass {
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PmuxtreePass() : Pass("pmuxtree", "transform $pmux cells to trees of $mux cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" pmuxtree [selection]\n");
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log("\n");
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log("This pass transforms $pmux cells to trees of $mux cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing PMUXTREE pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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for (auto cell : module->selected_cells())
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{
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if (cell->type != ID($pmux))
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continue;
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SigSpec sig_data = cell->getPort(ID::B);
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SigSpec sig_sel = cell->getPort(ID::S);
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if (!cell->getPort(ID::A).is_fully_undef()) {
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sig_data.append(cell->getPort(ID::A));
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SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel);
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sig_sel.append(module->Not(NEW_ID, sig_sel_or));
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}
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SigSpec result, result_or;
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result = recursive_mux_generator(module, sig_data, sig_sel, result_or);
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module->connect(cell->getPort(ID::Y), result);
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module->remove(cell);
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}
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}
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} PmuxtreePass;
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PRIVATE_NAMESPACE_END
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