mirror of
https://github.com/YosysHQ/yosys
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80 lines
2.6 KiB
C++
80 lines
2.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct DemuxmapPass : public Pass {
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DemuxmapPass() : Pass("demuxmap", "transform $demux cells to $eq + $mux cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" demuxmap [selection]\n");
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log("\n");
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log("This pass transforms $demux cells to a bunch of equality comparisons.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing DEMUXMAP pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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for (auto cell : module->selected_cells())
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{
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if (cell->type != ID($demux))
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continue;
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SigSpec sel = cell->getPort(ID::S);
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SigSpec data = cell->getPort(ID::A);
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SigSpec out = cell->getPort(ID::Y);
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int width = GetSize(cell->getPort(ID::A));
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for (int i = 0; i < 1 << GetSize(sel); i++) {
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if (width == 1 && data == State::S1) {
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RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]);
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eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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} else {
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Wire *eq = module->addWire(NEW_ID);
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RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq);
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eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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RTLIL::Cell *mux = module->addMux(NEW_ID,
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Const(State::S0, width),
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data,
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eq,
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out.extract(i*width, width));
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mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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}
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}
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module->remove(cell);
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}
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}
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} DemuxmapPass;
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PRIVATE_NAMESPACE_END
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