mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
103 lines
3.2 KiB
C++
103 lines
3.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct BmuxmapPass : public Pass {
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BmuxmapPass() : Pass("bmuxmap", "transform $bmux cells to trees of $mux cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" bmuxmap [selection]\n");
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log("\n");
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log("This pass transforms $bmux cells to trees of $mux cells.\n");
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log("\n");
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log(" -pmux\n");
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log(" transform to $pmux instead of $mux cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool pmux_mode = false;
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log_header(design, "Executing BMUXMAP pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-pmux") {
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pmux_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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for (auto cell : module->selected_cells())
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{
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if (cell->type != ID($bmux))
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continue;
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SigSpec sel = cell->getPort(ID::S);
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SigSpec data = cell->getPort(ID::A);
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int width = GetSize(cell->getPort(ID::Y));
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int s_width = GetSize(cell->getPort(ID::S));
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if(pmux_mode)
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{
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int num_cases = 1 << s_width;
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SigSpec new_a = SigSpec(State::Sx, width);
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SigSpec new_s = module->addWire(NEW_ID, num_cases);
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SigSpec new_data = module->addWire(NEW_ID, width);
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for (int val = 0; val < num_cases; val++)
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{
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module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]);
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}
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RTLIL::Cell *pmux = module->addPmux(NEW_ID, new_a, data, new_s, new_data);
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pmux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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data = new_data;
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}
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else
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{
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for (int idx = 0; idx < GetSize(sel); idx++) {
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SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
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for (int i = 0; i < GetSize(new_data); i += width) {
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RTLIL::Cell *mux = module->addMux(NEW_ID,
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data.extract(i*2, width),
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data.extract(i*2+width, width),
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sel[idx],
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new_data.extract(i, width));
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mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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}
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data = new_data;
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}
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}
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module->connect(cell->getPort(ID::Y), data);
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module->remove(cell);
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}
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}
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} BmuxmapPass;
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PRIVATE_NAMESPACE_END
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