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https://github.com/YosysHQ/yosys
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030d639201
Processes can contain `MemWriteAction` entries which are invisible to most passes operating on memories but which will be lowered to write ports later on by `proc_memwr`. For that reason we can get corrupted RTLIL if we sequence the memory passes before `proc`. Address that by making the affected memory passes ignore modules with processes.
70 lines
2.1 KiB
C++
70 lines
2.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryNarrowPass : public Pass {
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MemoryNarrowPass() : Pass("memory_narrow", "split up wide memory ports") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_narrow [options] [selection]\n");
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log("\n");
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log("This pass splits up wide memory ports into several narrow ports.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing MEMORY_NARROW pass (splitting up wide memory ports).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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if (module->has_processes_warn())
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continue;
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for (auto &mem : Mem::get_selected_memories(module))
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{
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bool wide = false;
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for (auto &port : mem.rd_ports)
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if (port.wide_log2)
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wide = true;
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for (auto &port : mem.wr_ports)
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if (port.wide_log2)
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wide = true;
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if (wide) {
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mem.narrow();
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mem.emit();
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}
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}
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}
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}
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} MemoryNarrowPass;
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PRIVATE_NAMESPACE_END
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