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Code
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49e1597ea4
yosys
/
tests
/
sim
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N. Engelhardt
2de9f00368
Merge pull request
#4620
from RCoeurjoly/fix-vcd-parsing-ghdl-var-spacing
2024-11-06 16:29:07 +01:00
..
tb
.gitignore
Added test cases
2022-02-16 13:27:59 +01:00
adff.v
adffe.v
adlatch.v
aldff.v
aldffe.v
assume_x_first_step.ys
dff.v
dffe.v
dffsr.v
dlatch.v
dlatchsr.v
run-test.sh
sdff.v
sdffce.v
sdffe.v
sim_adff.ys
sim_adffe.ys
sim_adlatch.ys
sim_aldff.ys
sim_aldffe.ys
sim_dff.ys
sim_dffe.ys
sim_dffsr.ys
sim_dlatch.ys
sim_dlatchsr.ys
sim_sdff.ys
sim_sdffce.ys
sim_sdffe.ys
simple_assign.v
simple_assign.vcd
var_reference_with_whitespace.vcd
var_reference_without_whitespace.vcd
vcd_var_reference_whitespace.ys
vector_assign.il