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yosys/passes/cmds
2026-03-18 00:44:20 +01:00
..
abstract.cc abstract: skip $input_port cells 2026-03-17 16:34:41 +01:00
add.cc
autoname.cc autoname.cc: Return number of renames 2025-09-26 11:05:50 +12:00
blackbox.cc
box_derive.cc Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
bugpoint.cc
check.cc check: stitch info about $connect ports together for driver analysis 2026-03-17 17:29:23 +01:00
chformal.cc signorm: disable in passes that use swap_names 2026-03-16 22:45:29 +01:00
chtype.cc
clean_zerowidth.cc
connect.cc
connwrappers.cc
copy.cc
cover.cc
delete.cc
design.cc design: fix signorm commit connectivity to design 2026-03-18 00:44:20 +01:00
dft_tag.cc
edgetypes.cc
example_dt.cc
exec.cc
future.cc
glift.cc
internal_stats.cc
linecoverage.cc Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
logcmd.cc
logger.cc
ltp.cc
Makefile.inc
plugin.cc
portarcs.cc portarcs: Ignore all bufnorm helper cells 2025-09-29 08:21:28 +02:00
portlist.cc
printattrs.cc
rename.cc flatten: redo signormalization to work around fanout issue 2026-03-17 18:04:41 +01:00
scatter.cc
scc.cc
scratchpad.cc
select.cc
setattr.cc
setenv.cc
setundef.cc
show.cc
splice.cc
splitcells.cc
splitnets.cc signorm: disable passes that use rewrite_sigspecs 2026-03-17 17:35:57 +01:00
sta.cc
stat.cc
tee.cc
test_select.cc
timeest.cc
torder.cc
trace.cc
viz.cc
wrapcell.cc
write_file.cc
xprop.cc