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https://github.com/YosysHQ/yosys
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44 lines
698 B
Verilog
44 lines
698 B
Verilog
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module test_signed(a, b, c, d, y);
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input [3:0] a, b, c;
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input signed [3:0] d;
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output reg [7:0] y;
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always @* begin
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if (a && b)
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y = c;
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else
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y = d;
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end
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endmodule
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module test_const(a, y);
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input [3:0] a;
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output reg [28:0] y;
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always @*
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case (a)
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4'b0000: y = 0;
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4'b0001: y = 11;
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4'b0010: y = 222;
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4'b0011: y = 3456;
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4'b0100: y = 'b10010010;
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4'b0101: y = 'h123abc;
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4'b0110: y = 'o1234567;
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4'b0111: y = 'd3456789;
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4'b1000: y = 16'b10010010;
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4'b1001: y = 16'h123abc;
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4'b1010: y = 16'o1234567;
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4'b1011: y = 16'd3456789;
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4'b1100: y = { "foo", "bar" };
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4'b1101: y = "foobarfoobarfoobar";
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4'b1110: y = 16'h1;
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4'b1111: y = a;
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default: y = 'bx;
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endcase
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endmodule
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