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57 lines
1 KiB
Verilog
57 lines
1 KiB
Verilog
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module mem2reg_test1(in_addr, in_data, out_addr, out_data);
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input [1:0] in_addr, out_addr;
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input [3:0] in_data;
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output reg [3:0] out_data;
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reg [3:0] array [2:0];
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always @* begin
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array[0] = 0;
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array[1] = 23;
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array[2] = 42;
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array[in_addr] = in_data;
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out_data = array[out_addr];
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end
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endmodule
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// ------------------------------------------------------
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module mem2reg_test2(clk, mode, addr, data);
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input clk, mode;
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input [2:0] addr;
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output [3:0] data;
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(* mem2reg *)
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reg [3:0] mem [0:7];
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assign data = mem[addr];
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integer i;
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always @(posedge clk) begin
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if (mode) begin
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for (i=0; i<8; i=i+1)
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mem[i] <= mem[i]+1;
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end else begin
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mem[addr] <= 0;
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end
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end
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endmodule
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// ------------------------------------------------------
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// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
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module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
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reg [7:0] dint_c [0:7];
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always @(posedge clk)
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begin
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{dout_a[0], dint_c[3]} <= din_a;
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end
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assign dout_b = dint_c[3];
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endmodule
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