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yosys/techlibs/ecp5
David Shah b424d374db ecp5: Fix shuffle_enable port
Signed-off-by: David Shah <dave@ds0.me>
2019-10-01 14:14:46 +01:00
..
tests
.gitignore ecp5: Add support for mapping 36-bit wide PDP BRAMs 2019-10-01 13:46:36 +01:00
abc_5g.box
abc_5g.lut
abc_5g_nowide.lut
abc_map.v
abc_model.v
abc_unmap.v
arith_map.v
bram.txt ecp5: Fix shuffle_enable port 2019-10-01 14:14:46 +01:00
brams_connect.py ecp5: Add support for mapping 36-bit wide PDP BRAMs 2019-10-01 13:46:36 +01:00
brams_init.py
brams_map.v ecp5: Add support for mapping 36-bit wide PDP BRAMs 2019-10-01 13:46:36 +01:00
cells_bb.v ecp5: Add support for mapping 36-bit wide PDP BRAMs 2019-10-01 13:46:36 +01:00
cells_ff.vh
cells_io.vh
cells_map.v
cells_sim.v
dsp_map.v
ecp5_ffinit.cc
ecp5_gsr.cc
latches_map.v
lutram.txt
lutrams_map.v
Makefile.inc ecp5: Add support for mapping 36-bit wide PDP BRAMs 2019-10-01 13:46:36 +01:00
synth_ecp5.cc Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once 2019-09-26 10:45:14 -07:00