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yosys/frontends
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Clifford Wolf 777f2881d8 Add Verilog "automatic" keyword (ignored in synthesis)
2017-11-23 08:51:38 +01:00
..
ast
blif
ilang
json
liberty
verific Remove all PSL support code from verific.cc 2017-10-20 13:14:04 +02:00
verilog Add Verilog "automatic" keyword (ignored in synthesis) 2017-11-23 08:51:38 +01:00