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79c5a06673
This primitive does not have a separate WRE port, so we regulate writing using Clock Enable. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.py | ||
| cells_xtra.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| Makefile.inc | ||
| synth_gowin.cc | ||