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.gitignore
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Add simple VHDL+PSL example
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2017-07-28 17:39:43 +02:00 |
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basic00.sv
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Improve SVA tests, add Makefile and scripts
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2017-07-27 11:42:05 +02:00 |
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basic01.sv
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Squelch a little more trailing whitespace
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2018-12-29 12:46:54 +01:00 |
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basic02.sv
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Improve SVA tests, add Makefile and scripts
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2017-07-27 11:42:05 +02:00 |
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basic03.sv
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Improve SVA tests, add Makefile and scripts
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2017-07-27 11:42:05 +02:00 |
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basic04.sv
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Improve SVA tests, add Makefile and scripts
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2017-07-27 11:42:05 +02:00 |
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basic04.vhd
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Improve SVA tests, add Makefile and scripts
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2017-07-27 11:42:05 +02:00 |
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basic05.sv
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Improve SVA tests, add Makefile and scripts
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2017-07-27 11:42:05 +02:00 |
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basic05.vhd
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Improve SVA tests, add Makefile and scripts
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2017-07-27 11:42:05 +02:00 |
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counter.sv
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Improve Verific SVA importer
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2017-07-27 14:05:09 +02:00 |
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extnets.sv
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Fix "verific -extnets" for more complex situations
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2019-03-26 14:17:46 +01:00 |
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Makefile
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Add simple VHDL+PSL example
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2017-07-28 17:39:43 +02:00 |
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runtest.sh
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Add support for SVA sequence concatenation ranges via verific
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2018-02-18 16:35:06 +01:00 |
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sva_not.sv
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Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
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2018-02-15 15:26:37 +01:00 |
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sva_range.sv
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Major redesign of Verific SVA importer
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2018-02-27 20:33:15 +01:00 |
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sva_throughout.sv
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Add support for SVA throughout via Verific
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2018-02-21 13:09:47 +01:00 |
