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yosys/techlibs/xilinx
2018-11-10 12:45:07 -08:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_bb.v
brams_init.py Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
brams_map.v
cells_map.v Improving vpr output support. 2018-04-18 16:55:12 -07:00
cells_sim.v
cells_xtra.sh Add support for Xilinx PS7 block 2018-11-10 12:45:07 -08:00
cells_xtra.v Add support for Xilinx PS7 block 2018-11-10 12:45:07 -08:00
drams.txt
drams_map.v
lut2lut.v
Makefile.inc
synth_xilinx.cc xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 2018-10-08 16:52:12 -07:00