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2025-10-24 08:24:35 +00:00
Code
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4722b07485
yosys
/
frontends
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N. Engelhardt
e47f5369fd
verificsva: check -L value is small enough for code to work
2025-07-09 15:58:35 +02:00
..
aiger
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
aiger2
aiger2: Clean debug print
2024-12-10 14:27:55 +01:00
ast
Merge pull request
#5163
from YosysHQ/emil/fix-single-bit-vector-leak
2025-06-04 17:00:54 +02:00
blif
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
json
fix handling of escaped chars in json backend and frontend
2022-02-18 17:13:09 +01:00
liberty
Liberty file caching with new
libcache
command
2025-04-03 13:39:35 +02:00
rpc
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
rtlil
read_rtlil: warn on assigns after switches in case rules
2024-11-21 22:41:13 +01:00
verific
verificsva: check -L value is small enough for code to work
2025-07-09 15:58:35 +02:00
verilog
verilog: add support for SystemVerilog string literals.
2025-07-03 20:51:12 -06:00