Krystine Sherwin 47202f51f3 Docs: Move verilog.rst to using_yosys ... Was previously in yosys_internals which is more developer focused, rather than user focused.		2025-03-22 14:18:57 +13:00
..
source	Docs: Move verilog.rst to using_yosys	2025-03-22 14:18:57 +13:00
tests	docs: Fix macro_commands	2024-05-10 09:51:37 +12:00
util	Docs: Render cell titles	2024-10-15 07:35:42 +13:00
.gitignore	Docs: Preliminary autocellgroup usage	2024-10-15 07:26:04 +13:00
Makefile	Makefile: Combine gen_images and gen_examples	2024-10-17 07:12:34 +13:00