mirror of
https://github.com/YosysHQ/yosys
synced 2025-12-23 04:33:46 +00:00
46cb05c471
When IdString refcounting was expensive, it made sense to pass it by const reference instead of by value, to avoid refcount churn. Now that IdString is not refcounted, it's slightly more efficient to pass it by value.
524 lines
15 KiB
C++
524 lines
15 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct BufnormPass : public Pass {
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BufnormPass() : Pass("bufnorm", "(experimental) convert design into buffered-normalized form") {
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experimental();
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}
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void help() override
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{
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log("\n");
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log(" bufnorm [options] [selection]\n");
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log("\n");
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log("Insert buffer cells into the design as needed, to make sure that each wire\n");
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log("has exactly one driving cell port, and aliasing wires are buffered using\n");
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log("buffer cells, than can be chained in a canonical order.\n");
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log("\n");
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log("Running 'bufnorm' on the whole design enters 'buffered-normalized mode'.\n");
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log("\n");
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log(" -buf\n");
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log(" Create $buf cells for all buffers. The default is to use $_BUF_ cells\n");
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log(" for sigle-bit buffers and $buf cells only for multi-bit buffers.\n");
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log("\n");
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log(" -chain\n");
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log(" Chain all alias wires. By default only wires with positive-valued\n");
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log(" 'chain' or 'keep' attribute on them are chained.\n");
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log("\n");
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log(" -output\n");
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log(" Enable chaining of ouput ports wires.\n");
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log("\n");
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log(" -public\n");
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log(" Enable chaining of wires wth public names.\n");
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log("\n");
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log(" -nochain\n");
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log(" Disable chaining of wires with 'chain' attribute.\n");
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log("\n");
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log(" -nokeep\n");
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log(" Disable chaining of wires with 'keep' attribute.\n");
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log("\n");
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log(" -flat\n");
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log(" Alias for -nokeep and -nochain.\n");
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log("\n");
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log(" -nosticky\n");
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log(" Disable 'sticky' behavior of output ports already driving whole\n");
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log(" wires, and always enforce canonical sort order instead.\n");
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log("\n");
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log(" -alphasort\n");
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log(" Strictly use alphanumeric sort for chain-order. (Default is\n");
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log(" to chain 'keep' wires first, then ports in declaration order,\n");
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log(" and then the other wires in alphanumeric sort order.)\n");
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log("\n");
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// log(" -noinit\n");
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// log(" Do not move 'init' attributes to the wires on FF output ports.\n");
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// log("\n");
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log("Run 'bufnorm' with -pos, -bits, or -conn on the whole design to remove all\n");
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log("$buf buffer cells and exit 'buffered-normalized mode' again.\n");
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log("\n");
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log(" -pos\n");
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log(" Create (multi- and single-bit) $pos cells instead $buf and $_BUF_.\n");
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log("\n");
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log(" -bits\n");
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log(" Create arrays of $_BUF_ cells instead of multi-bit $buf cells.\n");
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log("\n");
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log(" -conn\n");
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log(" Create 'direct connections' instead of buffer cells.\n");
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log("\n");
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log(" -nomode\n");
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log(" Do not automatically enter or leave 'buffered-normalized mode'.\n");
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log("\n");
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log("The 'bufnorm' command can also be used to just switch in and out of\n");
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log("'buffered-normalized mode' and run the low-level re-normalizer.\n");
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log("\n");
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log(" -update\n");
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log(" Enter 'buffered-normalized mode' and (re-)normalize.\n");
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log("\n");
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log(" -reset\n");
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log(" Leave 'buffered-normalized mode' without changing the netlist.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool buf_mode = false;
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bool chain_mode = false;
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bool output_mode = false;
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bool public_mode = false;
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bool nochain_mode = false;
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bool nokeep_mode = false;
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bool nosticky_mode = false;
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bool alphasort_mode = false;
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// bool noinit_mode = false; // FIXME: Actually move init attributes
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bool nomode_mode = false;
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bool pos_mode = false;
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bool bits_mode = false;
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bool conn_mode = false;
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bool update_mode = false;
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bool reset_mode = false;
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bool got_non_update_reset_opt = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-buf") {
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buf_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-chain") {
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chain_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-output") {
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output_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-public") {
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public_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-nochain") {
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nochain_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-nokeep") {
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nokeep_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-flat") {
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nochain_mode = true;
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nokeep_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-nosticky") {
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nosticky_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-alphasort") {
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alphasort_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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// if (arg == "-noinit") {
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// noinit_mode = true;
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// got_non_update_reset_opt = true;
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// continue;
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// }
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if (arg == "-pos") {
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pos_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-bits") {
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bits_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-conn") {
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conn_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-nomode") {
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nomode_mode = true;
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got_non_update_reset_opt = true;
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continue;
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}
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if (arg == "-update") {
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update_mode = true;
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continue;
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}
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if (arg == "-reset") {
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reset_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (buf_mode && pos_mode)
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log_cmd_error("Options -buf and -pos are exclusive.\n");
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if (buf_mode && conn_mode)
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log_cmd_error("Options -buf and -conn are exclusive.\n");
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if (pos_mode && conn_mode)
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log_cmd_error("Options -pos and -conn are exclusive.\n");
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if (update_mode && reset_mode)
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log_cmd_error("Options -update and -reset are exclusive.\n");
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if (update_mode && got_non_update_reset_opt)
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log_cmd_error("Option -update can't be mixed with other options.\n");
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if (reset_mode && got_non_update_reset_opt)
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log_cmd_error("Option -reset can't be mixed with other options.\n");
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if (update_mode) {
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design->bufNormalize();
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return;
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}
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if (reset_mode) {
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design->bufNormalize(false);
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return;
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}
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log_header(design, "Executing BUFNORM pass (convert to buffer-normalized form).\n");
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int count_removed_buffers = 0;
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int count_updated_buffers = 0;
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int count_kept_buffers = 0;
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int count_created_buffers = 0;
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int count_updated_cellports = 0;
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if (!nomode_mode && (pos_mode || bits_mode || conn_mode)) {
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if (design->selection().full_selection)
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design->bufNormalize(false);
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}
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for (auto module : design->selected_modules())
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{
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log("Buffer-normalizing module %s.\n", log_id(module));
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SigMap sigmap(module);
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module->new_connections({});
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dict<pair<IdString, SigSpec>, Cell*> old_buffers;
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{
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vector<Cell*> old_dup_buffers;
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for (auto cell : module->cells())
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{
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if (!cell->type.in(ID($buf), ID($_BUF_)))
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continue;
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SigSpec insig = cell->getPort(ID::A);
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SigSpec outsig = cell->getPort(ID::Y);
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for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++)
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sigmap.add(insig[i], outsig[i]);
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pair<IdString,Wire*> key(cell->type, outsig.as_wire());
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if (old_buffers.count(key))
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old_dup_buffers.push_back(cell);
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else
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old_buffers[key] = cell;
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}
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for (auto cell : old_dup_buffers)
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module->remove(cell);
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count_removed_buffers += GetSize(old_dup_buffers);
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}
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dict<SigBit, pool<Wire*>> bit2wires;
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dict<SigSpec, pool<Wire*>> whole_wires;
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dict<SigBit, SigBit> mapped_bits;
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pool<Wire*> unmapped_wires;
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for (auto wire : module->wires())
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{
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SigSpec keysig = sigmap(wire);
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whole_wires[keysig].insert(wire);
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for (auto keybit : sigmap(wire))
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bit2wires[keybit].insert(wire);
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if (wire->port_input) {
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log(" primary input: %s\n", log_id(wire));
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for (auto bit : SigSpec(wire))
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mapped_bits[sigmap(bit)] = bit;
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} else {
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unmapped_wires.insert(wire);
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}
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}
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auto chain_this_wire_f = [&](Wire *wire)
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{
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if (chain_mode)
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return true;
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if (output_mode && wire->port_output)
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return true;
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if (public_mode && wire->name.isPublic())
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return true;
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if (!nokeep_mode && wire->get_bool_attribute(ID::keep))
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return true;
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if (!nochain_mode && wire->get_bool_attribute(ID::chain))
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return true;
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return false;
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};
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auto compare_wires_f = [&](Wire *a, Wire *b)
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{
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// Chaining wires first, then flat wires
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bool chain_a = chain_this_wire_f(a);
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bool chain_b = chain_this_wire_f(b);
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if (chain_a != chain_b) return chain_a;
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if (!alphasort_mode)
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{
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// Wires with 'chain' attribute first, high values before low values
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if (!nochain_mode) {
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int chain_a_val = a->attributes.at(ID::chain, Const(0)).as_int();
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int chain_b_val = b->attributes.at(ID::chain, Const(0)).as_int();
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if (chain_a_val != chain_b_val) return chain_a_val > chain_b_val;
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}
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// Then wires with 'keep' attribute
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if (!nokeep_mode) {
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bool keep_a = a->get_bool_attribute(ID::keep);
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bool keep_b = b->get_bool_attribute(ID::keep);
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if (keep_a != keep_b) return keep_a;
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}
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// Ports before non-ports
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if ((a->port_id != 0) != (b->port_id != 0))
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return a->port_id != 0;
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// Ports in declaration order
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if (a->port_id != b->port_id)
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return a->port_id < b->port_id;
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}
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// Nets with public names first
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if (a->name.isPublic() != b->name.isPublic())
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return a->name.isPublic();
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// Otherwise just sort by name alphanumerically
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return a->name.str() < b->name.str();
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};
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID($buf), ID($_BUF_)))
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continue;
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for (auto &conn : cell->connections())
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{
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if (!cell->output(conn.first))
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continue;
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Wire *w = nullptr;
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if (!nosticky_mode && conn.second.is_wire())
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w = conn.second.as_wire();
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if (w == nullptr)
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{
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SigSpec keysig = sigmap(conn.second);
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auto it = whole_wires.find(keysig);
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if (it != whole_wires.end()) {
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it->second.sort(compare_wires_f);
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w = *(it->second.begin());
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} else {
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w = module->addWire(NEW_ID, GetSize(conn.second));
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for (int i = 0; i < GetSize(w); i++)
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sigmap.add(SigBit(w, i), keysig[i]);
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}
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}
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if (w->name.isPublic())
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log(" directly driven by cell %s port %s: %s\n",
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log_id(cell), log_id(conn.first), log_id(w));
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for (auto bit : SigSpec(w))
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mapped_bits[sigmap(bit)] = bit;
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unmapped_wires.erase(w);
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cell->setPort(conn.first, w);
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}
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}
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pool<Cell*> added_buffers;
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const auto lookup_mapping = [&mapped_bits](const SigBit bit, bool default_sx = false)
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{
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if (!bit.is_wire())
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return bit;
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if (default_sx)
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return mapped_bits.at(bit, State::Sx);
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return mapped_bits.at(bit);
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};
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auto make_buffer_f = [&](IdString type, const SigSpec &src, const SigSpec &dst)
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{
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auto it = old_buffers.find(pair<IdString, SigSpec>(type, dst));
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if (it != old_buffers.end())
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{
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Cell *cell = it->second;
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old_buffers.erase(it);
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added_buffers.insert(cell);
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if (cell->getPort(ID::A) == src) {
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count_kept_buffers++;
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} else {
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cell->setPort(ID::A, src);
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count_updated_buffers++;
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}
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return;
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}
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Cell *cell = module->addCell(NEW_ID, type);
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added_buffers.insert(cell);
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cell->setPort(ID::A, src);
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cell->setPort(ID::Y, dst);
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cell->fixup_parameters();
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count_created_buffers++;
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};
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unmapped_wires.sort(compare_wires_f);
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for (auto wire : unmapped_wires)
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{
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bool chain_this_wire = chain_this_wire_f(wire);
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SigSpec keysig = sigmap(wire), insig = wire, outsig = wire;
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for (int i = 0; i < GetSize(insig); i++)
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insig[i] = lookup_mapping(keysig[i], true);
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if (chain_this_wire) {
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for (int i = 0; i < GetSize(outsig); i++)
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mapped_bits[keysig[i]] = outsig[i];
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}
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log(" %s %s for %s -> %s\n",
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chain_this_wire ? "chaining" : "adding",
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conn_mode ? "connection" : "buffer",
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log_signal(insig), log_signal(outsig));
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if (conn_mode) {
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if (bits_mode) {
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for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++)
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module->connect(outsig[i], insig[i]);
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} else {
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module->connect(outsig, insig);
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}
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} else {
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if (bits_mode) {
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IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) : ID($_BUF_);
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for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++)
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make_buffer_f(celltype, insig[i], outsig[i]);
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} else {
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IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) :
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GetSize(outsig) == 1 ? ID($_BUF_) : ID($buf);
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make_buffer_f(celltype, insig, outsig);
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}
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}
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}
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for (auto &it : old_buffers)
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module->remove(it.second);
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count_removed_buffers += GetSize(old_buffers);
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for (auto cell : module->cells())
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{
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if (added_buffers.count(cell))
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continue;
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for (auto &conn : cell->connections())
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{
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if (cell->output(conn.first))
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continue;
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SigSpec newsig = conn.second;
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for (auto &bit : newsig)
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bit = lookup_mapping(sigmap(bit));
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if (conn.second != newsig) {
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log(" fixing input signal on cell %s port %s: %s\n",
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log_id(cell), log_id(conn.first), log_signal(newsig));
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cell->setPort(conn.first, newsig);
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count_updated_cellports++;
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}
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}
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}
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|
}
|
|
|
|
log("Summary: removed %d, updated %d, kept %d, and created %d buffers, and updated %d cell ports.\n",
|
|
count_removed_buffers, count_updated_buffers, count_kept_buffers,
|
|
count_created_buffers, count_updated_cellports);
|
|
|
|
if (!nomode_mode && !(pos_mode || bits_mode || conn_mode)) {
|
|
if (design->selection().full_selection)
|
|
design->bufNormalize(true);
|
|
}
|
|
}
|
|
} BufnormPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|