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yosys/tests/arch/xilinx
Marcelina Kościelnicka 8740fdf1d7 ast: Use better parameter serialization for paramod names.
Calling log_signal is problematic for several reasons:

- with recent changes, empty string is serialized as { }, which violates
  the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
  functionally different values and potentially introducing a subtle
  elaboration bug

Instead, use a custom simple serialization scheme.
2021-03-18 00:52:00 +01:00
..
.gitignore
abc9_dff.ys ast: Use better parameter serialization for paramod names. 2021-03-18 00:52:00 +01:00
add_sub.ys
adffs.ys
attributes_test.ys xilinx: Fix attributes_test.ys 2020-10-24 23:52:37 +02:00
blockram.ys
bug1460.ys
bug1462.ys
bug1480.ys
bug1598.ys
bug1605.ys
counter.ys
dffs.ys
dsp_abc9.ys xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 2020-09-23 09:15:24 -07:00
dsp_cascade.ys
dsp_fastfir.ys
dsp_simd.ys
fsm.ys synth_xilinx: Use opt_dff. 2020-07-30 22:26:09 +02:00
latches.ys opt_expr: Remove -clkinv option, make it the default. 2020-07-31 00:08:15 +02:00
logic.ys
lutram.ys
macc.sh
macc.v tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
macc.ys tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
macc_tb.v
mul.ys
mul_unsigned.v
mul_unsigned.ys
mux.ys xilinx_dffopt: Don't crash on missing IS_*_INVERTED. 2021-01-27 00:32:00 +01:00
mux_lut4.ys
nosrl.ys xilinx: Fix srl regression. 2020-07-12 23:41:27 +02:00
opt_lut_ins.ys
pmgen_xilinx_srl.ys satgen: Add support for dffe, sdff, sdffe, sdffce cells. 2020-07-24 03:19:21 +02:00
run-test.sh tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
shifter.ys
tribuf.sh
tribuf.ys
xilinx_dffopt.ys xilinx_dffopt: Don't crash on missing IS_*_INVERTED. 2021-01-27 00:32:00 +01:00
xilinx_dffopt_blacklist.txt
xilinx_dsp.ys
xilinx_srl.v
xilinx_srl.ys