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yosys/backends/verilog
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Emil J. Tywoniak 45452c18b2 write_verilog: write module ports in order
2025-05-14 14:34:50 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: write module ports in order 2025-05-14 14:34:50 +02:00