mirror of
https://github.com/YosysHQ/yosys
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4543751a77
sf2 ff have no initial values, but some IP cores use initial values. In order to use those cores on sf2, it is required to discard the initial value (to be carefully used).
265 lines
7.2 KiB
C++
265 lines
7.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthSf2Pass : public ScriptPass
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{
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SynthSf2Pass() : ScriptPass("synth_sf2", "synthesis for SmartFusion2 and IGLOO2 FPGAs") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_sf2 [options]\n");
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log("\n");
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log("This command runs synthesis for SmartFusion2 and IGLOO2 FPGAs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified EDIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -vlog <file>\n");
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log(" write the design to the specified Verilog file. writing of an output\n");
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log(" file is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -noiobs\n");
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log(" run synthesis in \"block mode\", i.e. do not insert IO buffers\n");
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log("\n");
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log(" -clkbuf\n");
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log(" insert direct PAD->global_net buffers\n");
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log("\n");
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log(" -discard-ffinit\n");
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log(" discard FF init value instead of emitting an error\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, edif_file, vlog_file, json_file;
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bool flatten, retime, iobs, clkbuf, discard_ffinit;
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void clear_flags() override
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{
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top_opt = "-auto-top";
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edif_file = "";
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vlog_file = "";
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json_file = "";
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flatten = true;
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retime = false;
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iobs = true;
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clkbuf = false;
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discard_ffinit = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-vlog" && argidx+1 < args.size()) {
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vlog_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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if (args[argidx] == "-noiobs") {
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iobs = false;
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continue;
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}
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if (args[argidx] == "-clkbuf") {
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clkbuf = true;
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continue;
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}
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if (args[argidx] == "-discard-ffinit") {
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discard_ffinit = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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log_header(design, "Executing SYNTH_SF2 pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib +/sf2/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (flatten && check_label("flatten", "(unless -noflatten)"))
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{
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run("proc");
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run("flatten");
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run("tribuf -logic");
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run("deminout");
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}
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if (check_label("coarse"))
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{
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if (discard_ffinit || help_mode)
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run("attrmap -remove init", "(only if -discard-ffinit)");
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run("synth -run coarse");
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}
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if (check_label("fine"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map");
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run("opt -undriven -fine");
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run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
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run("opt -fast");
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if (retime || help_mode)
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run("abc -dff -D 1", "(only if -retime)");
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}
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if (check_label("map_ffs"))
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{
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run("dfflegalize -cell $_DFFE_PN?P_ x -cell $_SDFFCE_PN?P_ x -cell $_DLATCH_PN?_ x");
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run("techmap -D NO_LUT -map +/sf2/cells_map.v");
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run("opt_expr -mux_undef");
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run("simplemap");
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// run("sf2_ffinit");
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// run("sf2_ffssr");
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// run("sf2_opt -full");
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}
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if (check_label("map_luts"))
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{
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run("abc -lut 4");
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run("clean");
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}
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if (check_label("map_cells"))
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{
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run("techmap -map +/sf2/cells_map.v");
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run("clean");
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}
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if (check_label("map_iobs"))
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{
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if (help_mode || iobs) {
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if (help_mode) {
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run("clkbufmap -buf CLKINT Y:A [-inpad CLKBUF Y:PAD]", "(unless -noiobs, -inpad only passed if -clkbuf)");
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} else if (clkbuf) {
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run("clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD");
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} else {
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run("clkbufmap -buf CLKINT Y:A");
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}
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run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs");
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}
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run("clean");
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}
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if (check_label("check"))
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{
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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run("blackbox =A:whitebox");
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}
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if (check_label("edif"))
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{
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if (!edif_file.empty() || help_mode)
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run(stringf("write_edif -gndvccy %s", help_mode ? "<file-name>" : edif_file.c_str()));
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}
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if (check_label("vlog"))
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{
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if (!vlog_file.empty() || help_mode)
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run(stringf("write_verilog %s", help_mode ? "<file-name>" : vlog_file.c_str()));
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}
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if (check_label("json"))
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{
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
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}
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}
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} SynthSf2Pass;
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PRIVATE_NAMESPACE_END
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