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yosys/techlibs/anlogic
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Icenowy Zheng c2b7ad3b28 anlogic: support BRAM mapping 
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-17 20:28:22 +08:00
..
.gitignore anlogic: support BRAM mapping 2021-12-17 20:28:22 +08:00
anlogic_eqn.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
anlogic_fixcarry.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
arith_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
brams.txt anlogic: support BRAM mapping 2021-12-17 20:28:22 +08:00
brams_init.py anlogic: support BRAM mapping 2021-12-17 20:28:22 +08:00
brams_map.v anlogic: support BRAM mapping 2021-12-17 20:28:22 +08:00
cells_map.v anlogic: Fix FF mapping. 2020-07-17 14:03:21 +02:00
cells_sim.v anlogic: Use dfflegalize. 2020-07-14 05:02:50 +02:00
eagle_bb.v Revert "Leave only real black box cells" 2018-12-17 23:20:40 +08:00
lutram_init_16x4.vh Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
lutrams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
lutrams_map.v Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
Makefile.inc anlogic: support BRAM mapping 2021-12-17 20:28:22 +08:00
synth_anlogic.cc anlogic: support BRAM mapping 2021-12-17 20:28:22 +08:00