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11 lines
324 B
Text
11 lines
324 B
Text
read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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#design -load postopt
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#shell
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