mirror of
https://github.com/YosysHQ/yosys
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c37db637c7
Primitives that are not planned for implementation for reasons of belonging to old unsupported chips or representing composite complex IPs rather than primitives are removed. Also latches and large MUXes not planned for implementation. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.py | ||
| cells_xtra_gw1n.v | ||
| cells_xtra_gw2a.v | ||
| cells_xtra_gw5a.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| Makefile.inc | ||
| synth_gowin.cc | ||