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30 lines
677 B
Verilog
30 lines
677 B
Verilog
/*
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Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89].
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*/
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// Unsigned 16x24-bit Multiplier
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// 1 latency stage on operands
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// 3 latency stage after the multiplication
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// File: multipliers2.v
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//
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module mul_unsigned (clk, A, B, RES);
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parameter WIDTHA = /*16*/ 6;
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parameter WIDTHB = /*24*/ 9;
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input clk;
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input [WIDTHA-1:0] A;
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input [WIDTHB-1:0] B;
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output [WIDTHA+WIDTHB-1:0] RES;
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reg [WIDTHA-1:0] rA;
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reg [WIDTHB-1:0] rB;
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reg [WIDTHA+WIDTHB-1:0] M [3:0];
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integer i;
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always @(posedge clk)
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begin
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rA <= A;
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rB <= B;
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M[0] <= rA * rB;
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for (i = 0; i < 3; i = i+1)
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M[i+1] <= M[i];
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end
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assign RES = M[3];
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endmodule
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