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https://github.com/YosysHQ/yosys
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129 lines
3.1 KiB
Text
129 lines
3.1 KiB
Text
design -reset
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read_verilog <<EOT
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module opt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
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always @(posedge clk) if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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select -assert-count 1 t:$dffe r:WIDTH=2 %i
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select -assert-count 0 t:$dffe %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
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always @(posedge clk) if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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wreduce
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select -assert-count 1 t:$dffe r:WIDTH=2 %i
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select -assert-count 0 t:$dffe %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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select -assert-count 1 t:$dffe r:WIDTH=2 %i
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select -assert-count 0 t:$dffe %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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select -assert-count 1 t:$dffe r:WIDTH=4 %i
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select -assert-count 0 t:$dffe %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o);
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always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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wreduce
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select -assert-count 1 t:$sdffe r:WIDTH=2 %i
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select -assert-count 0 t:$sdffe %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
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always @(posedge clk) begin
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if (ce) o <= i;
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if (!rstn) o <= 4'b1111;
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end
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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wreduce
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select -assert-count 1 t:$sdffe r:WIDTH=2 %i
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select -assert-count 0 t:$sdffe %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_signed_rst_init(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
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initial o <= 4'b0010;
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always @(posedge clk) begin
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if (ce) o <= i;
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if (!rstn) o <= 4'b1111;
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end
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endmodule
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EOT
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proc
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# NB: equiv_opt uses equiv_induct which covers
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# only the induction half of temporal induction
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# --- missing the base-case half
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# This makes it akin to `sat -tempinduct-inductonly`
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# instead of `sat -tempinduct-baseonly` or
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# `sat -tempinduct` which is necessary for this
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# testcase
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#equiv_opt -assert opt
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design -save gold
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opt
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wreduce
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -tempinduct -verify -prove-asserts -show-ports miter
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design -load gate
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select -assert-count 1 t:$sdffe r:WIDTH=3 %i
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select -assert-count 0 t:$sdffe %% t:* %D
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