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9 lines
313 B
Verilog
9 lines
313 B
Verilog
module wreduce_test0(input [7:0] a, b, output [15:0] x, y, z);
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assign x = -$signed({1'b0, a});
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assign y = $signed({1'b0, a}) + $signed({1'b0, b});
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assign z = x ^ y;
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endmodule
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module wreduce_test1(input [31:0] a, b, output [7:0] x, y, z, w);
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assign x = a - b, y = a * b, z = a >> b, w = a << b;
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endmodule
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