mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
e833c6a418
- Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
29 lines
575 B
Verilog
29 lines
575 B
Verilog
module pass_through_a(
|
|
input wire [31:0] inp,
|
|
output wire [31:0] out
|
|
);
|
|
assign out[31:0] = inp[31:0];
|
|
endmodule
|
|
|
|
module top_a(
|
|
input wire signed [31:0] inp,
|
|
output wire signed [31:0] out
|
|
);
|
|
pass_through_a pt(inp[31:0], out[31:0]);
|
|
endmodule
|
|
|
|
// tests both module declaration orderings
|
|
|
|
module top_b(
|
|
input wire signed [31:0] inp,
|
|
output wire signed [31:0] out
|
|
);
|
|
pass_through_b pt(inp[31:0], out[31:0]);
|
|
endmodule
|
|
|
|
module pass_through_b(
|
|
input wire [31:0] inp,
|
|
output wire [31:0] out
|
|
);
|
|
assign out[31:0] = inp[31:0];
|
|
endmodule
|